Imaging device, operating method thereof, and electronic device

ABSTRACT

An imaging device with low power consumption is provided. The pixel of the imaging device includes first and second photoelectric conversion elements, and first to fifth transistors. A cathode of the first photoelectric conversion element is electrically connected to the first transistor. An anode of a second photoelectric conversion element is electrically connected to the second transistor. Imaging data of a reference frame is obtained using the first photoelectric conversion element, and then imaging data of a difference detection frame is obtained using the second photoelectric conversion element. After the imaging data of the difference detection frame is obtained, a first potential that is a potential of a signal output from the pixel and a second potential that is a reference potential are compared. Whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined using the first potential and the second potential.

BACKGROUND OF THE INVENTION 1. Field of the Invention

One embodiment of the present invention relates to an imaging device, an operating method of the imaging device, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a light-emitting device, a power storage device, an imaging device, a memory device, a method for driving any of them, and a method for manufacturing any of them.

2. Description of the Related Art

A technique by which transistors are formed using oxide semiconductor thin films formed over a substrate has been attracting attention. For example, techniques for forming transistors using zinc oxide or an In—Ga—Zn-based oxide semiconductor as an oxide semiconductor are disclosed in Patent Documents 1 and 2.

Patent Document 3 discloses an imaging device in which a transistor including an oxide semiconductor and having an extremely low off-state current is used in part of a pixel circuit and a transistor including silicon with which a complementary metal oxide semiconductor (CMOS) circuit can be formed is used in a peripheral circuit.

In addition, Patent Document 4 discloses, as an imaging device that utilizes an avalanche multiplication phenomenon, an imaging device in which an amorphous semiconductor layer containing selenium as a main component is used for a photoelectric conversion element.

Moreover, Non-Patent Document 1 proposes an imaging device in which a photoelectric conversion element including a crystalline selenium thin film is formed over a CMOS circuit.

REFERENCE Patent Documents

-   [Patent Document 1] Japanese Published Patent Application No.     2007-123861 -   [Patent Document 2] Japanese Published Patent Application No.     2007-096055 -   [Patent Document 3] Japanese Published Patent Application No.     2011-119711 -   [Patent Document 4] Japanese Published Patent Application No.     2013-033664

Non-Patent Document

-   [Non-Patent Document 1] S. Imura et al., “High Sensitivity Image     Sensor Overlaid with Thin-Film Crystalline-Selenium-based     Heterojunction Photodiode,” International Electron Devices Meeting,     pp. 88-91, December 2014.

SUMMARY OF THE INVENTION

The power consumption in an imaging device can be reduced by decreasing the frequency of output of imaging data to an external device such as a display device. To achieve this, a method in which imaging data of one frame is compared with imaging data of the previous frame, and only when there is a difference between them, the imaging data of the one frame is output to an external device can be given, for example.

An object of one embodiment of the present invention is to provide an imaging device with low power consumption. Another object of one embodiment of the present invention is to provide a small-sized imaging device. Another object of one embodiment of the present invention is to provide an imaging device that can adjust light sensitivity. Another object of one embodiment of the present invention is to provide an imaging device that includes a transistor having a high on-state current. Another object of one embodiment of the present invention is to provide an imaging device that includes a transistor having a low off-state current. Another object of one embodiment of the present invention is to provide an imaging device that includes a transistor to which a high potential can be applied. Another object of one embodiment of the present invention is to provide an imaging device with a wide dynamic range. Another object of one embodiment of the present invention is to provide an imaging device with a long holding time of imaging data. Another object of one embodiment of the present invention is to provide an imaging device with which an image with little distortion can be easily obtained even when a subject moves. Another object of one embodiment of the present invention is to provide an imaging device that can be used at a wide temperature range. Another object of one embodiment of the present invention is to provide an imaging device that can obtain imaging data with little noise. Another object of one embodiment of the present invention is to provide an imaging device with high light sensitivity. Another object of one embodiment of the present invention is to provide an imaging device at low cost. Another object of one embodiment of the present invention is to provide an imaging device with high reliability.

Another object of one embodiment of the present invention is to provide a novel imaging device, a driving method of the imaging device, a novel electronic device, or the like.

Note that the objects of the present invention are not limited to the above objects. The objects described above do not disturb the existence of other objects. The other objects are the ones that are not described above and are described below. The other objects are apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention solves at least one of the above objects and the other objects.

One embodiment of the present invention is an imaging device including a first photoelectric conversion element, a second photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. A cathode of the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor. An anode of the second photoelectric conversion element is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and a gate of the fourth transistor. One of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor.

Each of the first to third transistors may include an oxide semiconductor in an active layer. The oxide semiconductor may contain In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

Each of the first photoelectric conversion element and the second photoelectric conversion element may contain a material containing selenium.

Another embodiment of the present invention is an imaging device including a first photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. A cathode of the first photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. An anode of the first photoelectric conversion element is electrically connected to one of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor. The other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the third transistor. The other of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the fourth transistor, one of a source and a drain of the fifth transistor, and a gate of the sixth transistor. One of a source and a drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor. The other of the source and the drain of the second transistor is electrically connected to a wiring. The wiring has a function of switching between a high potential and a low potential and supplying the corresponding potential.

Each of the first to fifth transistors may include an oxide semiconductor in an active layer. The oxide semiconductor may contain In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

The first photoelectric conversion element may contain a material containing selenium.

The imaging device of one embodiment of the present invention may further include a capacitor. One terminal of the capacitor may be electrically connected to the other of the source and the drain of the first transistor.

Another embodiment of the present invention is an operating method of an imaging device that includes a pixel including a first photoelectric conversion element and a second photoelectric conversion element. In the operating method, charge is accumulated in the pixel by reset operation, and then the charge corresponding to the illuminance of light with which the pixel is irradiated is released through the first photoelectric conversion element, and after that, the charge corresponding to the illuminance of light with which the pixel is irradiated is accumulated through the second photoelectric conversion element.

Another embodiment of the present invention is an electronic device including the imaging device of one embodiment of the present invention and a display device.

One embodiment of the present invention can provide an imaging device with low power consumption. Alternatively, a small-sized imaging device can be provided. Alternatively, an imaging device that can adjust light sensitivity can be provided. Alternatively, an imaging device that includes a transistor having a high on-state current can be provided. Alternatively, an imaging device that includes a transistor having a low off-state current can be provided. Alternatively, an imaging device that includes a transistor to which a high potential can be applied can be provided. Alternatively, an imaging device with a wide dynamic range can be provided. Alternatively, an imaging device with a long holding time of imaging data can be provided. Alternatively, an imaging device with which an image with little distortion can be easily obtained even when a subject moves can be provided. Alternatively, an imaging device that can be used at a wide temperature range can be provided. Alternatively, an imaging device that can obtain imaging data with little noise can be provided. Alternatively, an imaging device with high light sensitivity can be provided. Alternatively, an imaging device at low cost can be provided. Alternatively, an imaging device with high reliability can be provided.

Another embodiment of the present invention can provide a novel imaging device, a novel operation method of an imaging device, a novel electronic device, or the like.

Note that the effects of one embodiment of the present invention are not limited to the above effects. The effects described above do not disturb the existence of other effects. The other effects are the ones that are not described above and are described below. The other effects are apparent from and can be derived from the description of the specification, the drawings, and the like by those skilled in the art. One embodiment of the present invention has at least one of the above effects and the other effects. Accordingly, one embodiment of the present invention does not have the aforementioned effects in some cases.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a pixel circuit of an imaging device.

FIG. 2 is a timing chart illustrating imaging operation.

FIG. 3 is a timing chart illustrating imaging operation.

FIG. 4 is a timing chart illustrating imaging operation.

FIG. 5 is a timing chart illustrating imaging operation.

FIG. 6 is a block diagram illustrating an imaging device.

FIG. 7 illustrates a pixel circuit and a difference detection circuit.

FIG. 8 is a flowchart showing an operation method of an imaging device.

FIG. 9 is a flowchart showing an operation method of an imaging device.

FIG. 10 illustrates a pixel circuit of an imaging device.

FIG. 11 is a timing chart illustrating imaging operation.

FIG. 12 is a timing chart illustrating imaging operation.

FIG. 13 is a timing chart illustrating imaging operation.

FIG. 14 is a timing chart illustrating imaging operation.

FIG. 15 illustrates a pixel circuit of an imaging device.

FIGS. 16A and 16B each illustrate a pixel circuit of an imaging device.

FIG. 17 is a timing chart illustrating imaging operation.

FIG. 18 is a timing chart illustrating imaging operation.

FIG. 19 is a timing chart illustrating imaging operation.

FIG. 20 is a timing chart illustrating imaging operation.

FIG. 21 illustrates a pixel circuit of an imaging device.

FIG. 22 illustrates a pixel circuit of an imaging device.

FIGS. 23A and 23B each illustrate a pixel circuit of an imaging device.

FIG. 24 illustrates a pixel circuit of an imaging device.

FIG. 25 illustrates a pixel circuit of an imaging device.

FIGS. 26A and 26B illustrate operations of a rolling shutter system and a global shutter system.

FIGS. 27A to 27F each illustrate a pixel circuit of an imaging device.

FIGS. 28A and 28B are each a timing chart illustrating imaging operation.

FIGS. 29A and 29B each illustrate a pixel circuit of an imaging device.

FIGS. 30A to 30C are each a cross-sectional view illustrating a structure of an imaging device.

FIGS. 31A and 31B are each a cross-sectional view illustrating a structure of an imaging device.

FIG. 32 is a cross-sectional view illustrating a structure of an imaging device.

FIGS. 33A to 33F are each a cross-sectional view illustrating a structure of an imaging device.

FIG. 34 is a cross-sectional view illustrating a structure of an imaging device.

FIGS. 35A to 35C are cross-sectional views and a circuit diagram illustrating the structures of imaging devices.

FIGS. 36A and 36B are each a cross-sectional view illustrating a structure of an imaging device.

FIG. 37 is a cross-sectional view illustrating a structure of an imaging device.

FIG. 38 is a cross-sectional view illustrating a structure of an imaging device.

FIGS. 39A to 39C are each a cross-sectional view illustrating a structure of an imaging device.

FIG. 40 is a cross-sectional view illustrating a structure of an imaging device.

FIG. 41 is a cross-sectional view illustrating a structure of an imaging device.

FIG. 42 is a cross-sectional view illustrating a structure of an imaging device.

FIG. 43 is a cross-sectional view illustrating a structure of an imaging device.

FIGS. 44A1, 44A2, 44A3, 44B1, 44B2, and 44B3 illustrate bent imaging devices.

FIGS. 45A to 45F are top views and cross-sectional views illustrating transistors.

FIGS. 46A to 46F are top views and cross-sectional views illustrating transistors.

FIGS. 47A to 47D each illustrate a cross section of a transistor in a channel width direction.

FIGS. 48A to 48E are a top view and cross-sectional views illustrating an oxide semiconductor layer.

FIGS. 49A to 49F are top views and cross-sectional views illustrating a transistor.

FIGS. 50A to 50F are top views and cross-sectional views illustrating a transistor.

FIGS. 51A to 51D each illustrate a cross section of a transistor in a channel width direction.

FIGS. 52A to 52F each illustrate a cross section of a transistor in a channel length direction.

FIGS. 53A to 53F each illustrate a cross section of a transistor in a channel length direction.

FIGS. 54A to 54C are a top view and cross-sectional views illustrating a transistor.

FIGS. 55A to 55C are each a top view illustrating a transistor.

FIGS. 56A to 56E show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD and selected-area electron diffraction patterns of a CAAC-OS.

FIGS. 57A to 57E show a cross-sectional TEM image and plan-view TEM images of a CAAC-OS and images obtained through analysis thereof.

FIGS. 58A to 58D show electron diffraction patterns and a cross-sectional TEM image of an nc-OS.

FIGS. 59A and 59B show cross-sectional TEM images of an a-like OS.

FIG. 60 shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation.

FIGS. 61A to 61D are perspective views and a cross-sectional view illustrating a package including an imaging device.

FIGS. 62A to 62D are perspective views and a cross-sectional view illustrating a package including an imaging device.

FIGS. 63A to 63F illustrate electronic devices.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments are described in detail with reference to drawings. Note that the present invention is not limited to the following description and it is readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated in some cases. The same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases.

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such a scale. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. For example, variations in signal, voltage, or current due to noise or difference in timing can be included.

In this specification and the like, a transistor is an element having at least three terminals: a gate, a drain, and a source. The transistor includes a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode) and current can flow through the drain, the channel region, and the source.

Since the source and the drain of the transistor change depending on the structure, operating conditions, and the like of the transistor, it is difficult to define which is a source or a drain. Thus, the terms “source” and “drain” can be interchanged with each other depending on the case or circumstances.

In this specification, ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion among components, and thus do not limit the number of the components.

In this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without limitation to a predetermined connection relation, for example, a connection relation shown in drawings or text, another connection relation is included in the drawings or the text.

Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive layer, and a layer).

Examples of the case where X and Y are directly connected include the case where an element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) is not connected between X and Y, and the case where X and Y are connected without the element that enables electrical connection between X and Y provided therebetween.

For example, in the case where X and Y are electrically connected, one or more elements that enable electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, and a load) can be connected between X and Y. Note that the switch is controlled to be turned on or off. That is, a switch is conducting or not conducting (is turned on or off) to determine whether current flows therethrough or not. Alternatively, the switch has a function of selecting and changing a current path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

For example, in the case where X and Y are functionally connected, one or more circuits that enable functional connection between X and Y (e.g., a logic circuit such as an inverter, a NAND circuit, or a NOR circuit; a signal converter circuit such as a DA converter circuit, an AD converter circuit, or a gamma correction circuit; a potential level converter circuit such as a power supply circuit (e.g., a step-up circuit or a step-down circuit) or a level shifter circuit for changing the potential level of a signal; a voltage source; a current source; a switching circuit; an amplifier circuit such as a circuit capable of increasing signal amplitude, the amount of current, or the like, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit; a signal generation circuit; a memory circuit; and/or a control circuit) can be connected between X and Y. For example, in the case where a signal output fromX is transmitted to Y even when another circuit is placed between X and Y, X and Y are functionally connected. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the description “X and Y are connected.”

For example, any of the following expressions can be used for the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) ZT and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to one part of Z1 and another part of Z1 is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to one part of Z2 and another part of Z2 is directly connected to Y.

Examples of the expressions include “X, Y, a source (or a first terminal or the like) of a transistor, and a drain (or a second terminal or the like) of the transistor are electrically connected to each other, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order,” “a source (or a first terminal or the like) of a transistor is electrically connected to X, a drain (or a second terminal or the like) of the transistor is electrically connected to Y, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are electrically connected to each other in this order,” and “X is electrically connected to Y through a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor, and X, the source (or the first terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor, and Y are provided to be connected in this order.” When the connection order in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Other examples of the expressions include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1 is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2 is on the third connection path.” Another example of the expression is “a source (or a first terminal or the like) of a transistor is electrically connected to X at least with a first connection path through Z1, the first connection path does not include a second connection path, the second connection path includes a connection path through which the transistor is provided, a drain (or a second terminal or the like) of the transistor is electrically connected to Y at least with a third connection path through Z2, and the third connection path does not include the second connection path.” Still another example of the expression is “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least ZT on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least Z2 on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor.” When the connection path in a circuit configuration is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Note that these expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2 each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive layer, and a layer).

Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring functions as an electrode, one conductive layer functions as the wiring and the electrode. Thus, “electrical connection” in this specification includes in its category such a case where one conductive layer has functions of a plurality of components.

Note that in this specification, terms for explaining arrangement, such as “over” and “under,” are used for convenience to describe the positional relationship between components with reference to drawings. The positional relationship between components is changed as appropriate in accordance with a direction in which each component is described. Thus, there is no limitation on terms used in this specification, and description can be made appropriately depending on the situation.

The positional relation of circuit blocks in a block diagram is specified for description. Even when a block diagram shows that different functions are achieved by different circuit blocks, one circuit block may be actually configured to achieve different functions. Functions of circuit blocks in a diagram are specified for description, and even when a diagram shows one circuit block performing given processing, a plurality of circuit blocks may be actually provided to perform the processing.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. The term “insulating film” can be changed into the term “insulating layer” in some cases.

Embodiment 1

An imaging device of one embodiment of the present invention is described with reference to drawings.

In this specification and the like, an imaging device refers to any device that has an imaging function. The imaging device also indicates a circuit having a function of imaging or an entire system including such a circuit.

One embodiment of the present invention relates to an imaging device having a difference detection function. The difference detection function means a function of comparing imaging data of one frame with imaging data of the previous frame and detecting whether or not there is a difference between them. Thus, by assuming that an object in one frame is moved when there is a difference, for example, motion of the object can be detected. Imaging data is output to an external device only when there is a difference, that is, only when motion of an object is detected; thus, as compared with a case where imaging data of all frames is output to an external device, power consumption can be reduced, for example.

In this specification, a device provided outside an imaging device is referred to as an external device. As an example of the external device, a display device can be given.

FIG. 1 illustrates a circuit diagram of a pixel 10 included in an imaging device that is one embodiment of the present invention. The pixel 10 includes a photoelectric conversion element 20 a, a photoelectric conversion element 20 b, a transistor 31 a, a transistor 31 b, a transistor 32, a transistor 33, a transistor 34, and a capacitor 41. Note that the transistors 31 a, 31 b, and 32 to 34 in FIG. 1 are all n-channel transistors.

Note that in this specification, an n-channel transistor may be referred to as an n-ch transistor, and a p-channel transistor may be referred to as a p-ch transistor.

In the pixel 10 in FIG. 1 , a cathode of the photoelectric conversion element 20 a is electrically connected to one of a source and a drain of the transistor 31 a. An anode of the photoelectric conversion element 20 b is electrically connected to one of a source and a drain of the transistor 31 b. The other of the source and the drain of the transistor 31 a is electrically connected to the other of the source and the drain of the transistor 31 b, one of a source and a drain of the transistor 32, a gate of the transistor 33, and one terminal of the capacitor 41. One of a source and a drain of the transistor 33 is electrically connected to one of a source and a drain of the transistor 34.

An anode of the photoelectric conversion element 20 a is electrically connected to a wiring 51 a (VPDa). A cathode of the photoelectric conversion element 20 b is electrically connected to a wiring 51 b (VPDb). The other of the source and the drain of the transistor 32 is electrically connected to a wiring 52 (VR). The other terminal of the capacitor 41 is electrically connected to a wiring 53 (VSS). The other of the source and the drain of the transistor 34 is electrically connected to a wiring 54 (VPI). The other of the source and the drain of the transistor 33 is electrically connected to a wiring 55 (VOUT).

A gate of the transistor 31 a is electrically connected to a wiring 61 a (TXa). A gate of the transistor 31 b is electrically connected to a wiring 61 b (TXb). A gate of the transistor 32 is electrically connected to a wiring 62 (RES). A gate of the transistor 34 is electrically connected to a wiring 64 (SEL).

The wirings 51 a (VPDa), 51 b (VPDb), 52 (VR), 53 (VSS), and 54 (VPI) can serve as power supply lines. In contrast, the wiring 61 a (TXa), 61 b (TXb), 62 (RES), and 64 (SEL) can serve as signal lines.

In the above-described structure, a node to which the other of the source and the drain of the transistor 31 a, the other of the source and the drain of the transistor 31 b, the one of the source and the drain of the transistor 32, the gate of the transistor 33, and the one terminal of the capacitor 41 are connected is a node FD.

In the pixel 10, the photoelectric conversion elements 20 a and 20 b are light-receiving elements and have a function of generating current corresponding to the illuminance of light with which the pixel 10 is irradiated. The transistor 31 a has a function of controlling the release of charge from the node FD to the photoelectric conversion element 20 a. The amount of the charge depends on the illuminance of light with which the pixel 10 is irradiated. The transistor 31 b has a function of controlling the accumulation of charge from the photoelectric conversion element 20 b to the node FD. The amount of the charge depends on the illuminance of light with which the pixel 10 is irradiated. The transistor 32 has a function of resetting the potential of the node FD. The transistor 33 serves as an amplifying transistor that outputs a signal corresponding to the potential of the node FD. The transistor 34 serves as a selection transistor that controls selection of the pixel 10 in reading.

Imaging data obtained by the pixel 10 is output as a signal via the wiring 55 (VOUT).

As described above, in the pixel included in the imaging device of one embodiment of the present invention, the cathode of the photoelectric conversion element 20 a is electrically connected to the one of the source and the drain of the transistor 31 a, and the anode of the photoelectric conversion element 20 b is electrically connected to the one of the source and the drain of the transistor 31 b. With the pixel having the configuration, the imaging device of one embodiment of the present invention can be operated in a normal imaging mode or a difference detection mode. The normal imaging mode is a mode in which imaging data obtained by the pixel 10 illustrated in FIG. 1 is output to an external device. The difference detection mode, which is described in detail later, is a mode in which imaging data of a difference detection frame is obtained after imaging data of a reference frame is obtained, and whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame is determined in accordance with the potential of a signal that is output after the imaging data of the difference detection frame is obtained. In the difference detection mode, by assuming that an object in one frame is moved when there is a difference, for example, motion of the object can be detected.

Note that the pixel 10 having the configuration illustrated in FIG. 1 may be referred to as an integration type pixel.

Next, the operation of the pixel 10 illustrated in FIG. 1 is described in detail with reference to timing charts of FIG. 2 , FIG. 3 , FIG. 4 , and FIG. 5 . The timing charts show the potentials of the wirings 61 a (TXa), 61 b (TXb), 62 (RES), and 64 (SEL) and the node FD.

Note that when the pixel 10 is operated on the basis of the timing charts shown in FIG. 2 and FIG. 3 , the potentials of the wirings 51 b (VPDb), 52 (VR), and 54 (VPI) are set at an H level, and the potentials of the wirings 51 a (VPDa) and 53 (VSS) are set at an L level.

In this specification, the H level refers to a high potential and the L level refers to a low potential. The L level can be a ground potential, for example.

The operation of the pixel 10 in the normal imaging mode is described with reference to the timing chart of FIG. 2 . Imaging data of the first frame is obtained and read in a period from time T01 to time T05, and imaging data of the second frame is obtained and read in a period from time T11 to time T15.

At Time T01, the potentials of the wirings 61 a (TXa) and 62 (RES) are set at the H level, whereby the transistors 31 a and 32 are turned on. Furthermore, the potentials of the wirings 61 b (TXb) and 64 (SEL) are set at the L level, whereby the transistors 31 b and 34 are turned off. Accordingly, the potential of the node FD is set to the potential VR of the wiring 52 (VR).

At Time T02, the potential of the wiring 62 (RES) is set at the L level, whereby the transistor 32 is turned off. As a result, the potential of the node FD starts to decrease. As the illuminance of light with which the pixel 10 is irradiated becomes higher, the potential of the node FD decreases greatly.

At time T03, the potential of the wiring 61 a (TXa) is set at the L level, whereby the transistor 31 a is turned off. As a result, the potential of the node FD is held. Through the above operation, the imaging data of the first frame is obtained.

At Time T04, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). Note that the signal corresponds to the imaging data obtained in the period from Time T01 to Time T03. Note that the lower the potential of the node FD is, the lower the potential of the signal that is output from the wiring 55 (VOUT) becomes. In other words, the higher the luminance of light with which the pixel 10 is irradiated is, the lower the potential of the signal output from the wiring 55 (VOUT) becomes.

At Time T05, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the first frame is read and output to the external device.

The operation in the period from Time T11 to Time T15 is similar to that in the period from Time T01 to Time T05. In this manner, the operation in the period from Time T01 to Time T05 is repeated in the normal imaging mode.

Next, the operation of the pixel 10 in the difference detection mode is described with reference to the timing chart of FIG. 3 .

A period from Time T101 to Time T103 corresponds to a period for obtaining the imaging data of the reference frame. The operation in the period from Time T101 to Time T103 is similar to that in the period from Time T01 to Time T03 shown in FIG. 2 .

A period from Time T111 to Time T114 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is no difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T111 to Time T112 is the same as that in the period from Time T102 to Time T103.

At Time T111, the potential of the wiring 61 b (TXb) is set at the H level, whereby the transistor 31 b is turned on. Furthermore, at time T112, the potential of the wiring 61 b (TXb) is set at the L level, whereby the transistor 31 b is turned off. Through the above operation, the imaging data of the difference detection frame is obtained.

Since the one of the source and the drain of the transistor 31 b is electrically connected to the anode of the photoelectric conversion element 20 b and the H level potential is applied to the cathode of the photoelectric conversion element 20 b, the potential of the node FD is raised in the period from Time T111 to Time T112 by irradiating the pixel 10 with light. Here, it is assumed that, if the illuminance of light with which the pixel 10 is irradiated is the same, the amount of charge per unit time flowing through the photoelectric conversion element 20 a in the case where the transistor 31 a is turned on is the same as that flowing through the photoelectric conversion element 20 b in the case where the transistor 31 b is turned on, regardless of the potential of the node FD. Furthermore, it is assumed that the length of a period from Time T102 to Time T103 is the same as that between Time T111 and Time T112. Under the above conditions, the potential of the node FD is raised to the potential VR at Time T112.

Note that although it is assumed here that the length of the period from Time T102 to Time T103 is the same as the length of the period from Time T111 to Time T112, the essence of one embodiment of the present invention is to set the lengths so that a decrease in the potential of the node FD in the period from Time T102 to Time T103 is the same as an increase of the potential of the node FD in the period from Time T111 to Time T112 in the case where the illuminance of light with which the pixel 10 is irradiated is the same. Thus, in order to satisfy the above condition, the length of the period from Time T102 and Time T103 and the length of the period from Time T111 and Time T112 are preferably adjusted as appropriate.

At Time T113, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). The potential of the signal is the potential in the case where a potential of the node FD is equal to the potential VR.

At Time T114, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the difference detection frame is read.

A period from Time T201 to Time T203 corresponds to a period for obtaining the imaging data of the reference frame again. The operation in the period from Time T201 to Time T203 is similar to that in the period from Time T101 to Time T103.

A period from Time T211 to Time T214 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T211 to Time T212 is higher than that in the period from Time T202 to Time T203.

The operation in the period from Time T211 to Time T214 is similar to that in the period from Time T111 to Time T114. Since the illuminance of light with which the pixel 10 is irradiated in the period from Time T211 to Time T212 is higher than that in the period from Time T202 to Time T203, the potential of the node FD at Time T212 is higher than the potential VR of the node FD at Time T202. Thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T213 to Time T214 is higher than the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR.

A period from Time T301 to Time T303 corresponds to a period for obtaining the imaging data of the reference frame again. The operation in the period from Time T301 to Time T303 is similar to that in the period from Time T201 to Time T203.

A period from Time T311 to Time T314 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T311 to Time T312 is lower than that in the period from Time T302 to Time T303.

The operation in the period from Time T311 to Time T314 is similar to that in the period from Time T211 to Time T214. Since the illuminance of light with which the pixel 10 is irradiated in the period from Time T311 to Time T312 is lower than that in the period from Time T302 to Time T303, the potential of the node FD at Time T312 is lower than the potential VR of the node FD at Time T302. Thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T313 to Time T314 is lower than the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR.

As described above, in the difference detection mode, the imaging data of the reference frame and the imaging data of the difference detection frame are alternately obtained. When there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame, the potential of the node FD is different from the potential VR. Thus, the potential of the signal output from the wiring 55 (VOUT) after the imaging data of the difference detection frame is obtained is different from the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR. In contrast, when there is no difference between the imaging data of the reference frame and the imaging data of the difference detection frame, the potential of the node FD is the same as the potential VR. Thus, the potential of the signal output from the wiring 55 (VOUT) after the imaging data of the difference detection frame is obtained is the same as the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR.

As described above, from the potential of the signal output from the wiring 55 (VOUT) after the imaging data of the difference detection frame is obtained, whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame can be determined.

Note that although the imaging data of the reference frame is not output to the external device in the operation shown in the timing chart of FIG. 3 , the imaging data of the reference frame may be output to the external device as in the normal imaging mode. In this case, after the operation at Time T103, Time T203, or Time T303 is terminated, operation similar to the operation at Time T04 and Time T05 shown in FIG. 2 is performed.

The pixel 10 shown in FIG. 1 can also be operated while the potentials of the wirings 51 b (VPDb), 53 (VSS), and 54 (VPI) are set at the H level and the potentials of the wirings 51 a (VPDa) and 52 (VR) are set at the L level. The operation of the pixel 10 in this case is described with reference to the timing charts in FIG. 4 and FIG. 5 .

FIG. 4 is a timing chart showing the operation of the pixel 10 in the normal imaging mode. Imaging data of the first frame is obtained and read in a period from time T01 to time T05, and imaging data of the second frame is obtained and read in a period from time T11 to time T15.

At Time T01, the potentials of the wirings 61 b (TXb) and 62 (RES) are set at the H level, whereby the transistors 31 b and 32 are turned on. Furthermore, the potentials of the wirings 61 a (TXa) and 64 (SEL) are set at the L level, whereby the transistors 31 a and 34 are turned off. Accordingly, the potential of the node FD is set to the potential VR of the wiring 52 (VR).

At Time T02, the potential of the wiring 62 (RES) is set at the L level, whereby the transistor 32 is turned off. Since the potential VPDb of the wiring 51 b (VPDb) is at the H level and the potential VR of the wiring 52 (VR) is at the L level; thus, the potential of the node FD is raised. As the illuminance of light with which the pixel is irradiated becomes higher, the potential of the node FD rises greatly.

At time T03, the potential of the wiring 61 b (TXb) is set at the L level, whereby the transistor 31 b is turned off. As a result, the potential of the node FD is held. Through the above operation, the imaging data of the first frame is obtained.

At Time T04, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). Note that the signal corresponds to the imaging data obtained in the period from Time T01 to Time T03. Note that the higher the potential of the node FD is, the higher the potential of the signal that is output from the wiring 55 (VOUT) becomes. In other words, the higher the luminance of light with which the pixel 10 is irradiated is, the higher the potential of the signal output from the wiring 55 (VOUT) becomes.

At Time T05, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the first frame is read and output to the external device.

The operation in the period from Time T11 to Time T15 is similar to that in the period from Time T01 to Time T05. The above is the operation in the normal imaging mode.

FIG. 5 is a timing chart showing the operation of the pixel 10 in the difference detection mode. A period from Time T101 to Time T103, a period from Time T201 to Time T203, and a period from Time T301 to Time T303 each correspond to a period for obtaining the imaging data of the reference frame. The operation in each of the periods is similar to that in the period from Time T01 to Time T03 in FIG. 4 .

A period from Time T111 to Time T114 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is no difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T111 to Time T112 is the same as that in the period from Time T102 to Time T103.

At Time T111, the potential of the wiring 61 a (TXa) is set at the H level, whereby the transistor 31 a is turned on. Furthermore, at time T112, the potential of the wiring 61 a (TXa) is set at the L level, whereby the transistor 31 a is turned off. Through the above operation, the imaging data of the difference detection frame is obtained.

Since the one of the source and the drain of the transistor 31 a is electrically connected to the cathode of the photoelectric conversion element 20 a and the L level potential is applied to the anode of the photoelectric conversion element 20 a, the potential of the node FD is decreased in the period from Time T111 to Time T112 by irradiating the pixel 10 with light. Here, it is assumed that, if the illuminance of light with which the pixel 10 is irradiated is the same, the amount of charge per unit time flowing through the photoelectric conversion element 20 a in the case where the transistor 31 a is turned on is the same as that flowing through the photoelectric conversion element 20 b in the case where the transistor 31 b is turned on, regardless of the potential of the node FD. Furthermore, it is assumed that the length of the period from Time T102 to Time T103 is the same as the length of the period from Time T111 to Time T112. Under the conditions, the potential of the node FD is decreased to the potential VR at Time T112.

Note that although it is assumed here that the length of the period from Time T102 to Time T103 is the same as that between Time T111 and Time T112, the essence of one embodiment of the present invention is to set the lengths so that an increase in the potential of the node FD in the period from Time T102 to Time T103 is the same as a decrease of the potential of the node FD in the period from Time T111 to Time T112. Thus, in order to satisfy the above condition, the length of the period from Time T102 to Time T103 and the length of the period from Time T111 to Time T112 are preferably adjusted as appropriate.

At Time T113, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). The potential of the signal is the potential in the case where a potential of the node FD is equal to the potential VR.

At Time T114, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the difference detection frame is read.

A period from Time T211 to Time T214 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T211 to Time T212 is higher than that in the period from Time T202 to Time T203.

The operation in the period from Time T211 to Time T214 is similar to that in the period from Time T111 to Time T114. Since the illuminance of light with which the pixel 10 is irradiated in the period from Time T211 to Time T212 is higher than that in the period from Time T202 to Time T203, the potential of the node FD at Time T212 is lower than the potential VR of the node FD at Time T202. Thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T213 to Time T214 is lower than the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR.

The period from Time T311 to Time T314 corresponds to a period during which the imaging data of the difference detection frame is obtained and read in the case where there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame. Note that the illuminance of light with which the pixel 10 is irradiated in the period from Time T311 to Time T312 is lower than that in the period from Time T302 to Time T303.

The operation in the period from Time T311 to Time T314 is similar to that in the period from Time T211 to Time T214. Since the illuminance of light with which the pixel 10 is irradiated in the period from Time T311 to Time T312 is lower than that in the period from Time T302 to Time T303, the potential of the node FD at Time T312 is higher than the potential VR of the node FD at Time T302. Thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T313 to Time T314 is higher than the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD is the potential VR.

The above is the operation in the difference detection mode. Note that although the imaging data of the reference frame is not output to the external device in the operation shown in the timing chart of FIG. 5 , the imaging data of the reference frame may be output to the external device as in the normal imaging mode. In this case, after the operation at Time T103, Time T203, or Time T303 is terminated, operation similar to the operation at Time T04 and Time T05 shown in FIG. 4 is performed.

FIG. 6 is a block diagram illustrating the imaging device of one embodiment of the present invention. The imaging device includes pixels 10, a circuit 12, a circuit 13, a circuit 14, and a circuit 15. The pixels 10 are arranged in matrix to form a pixel array 11.

Note that although the circuits 15 are provided column by column in the pixel array 11 of FIG. 6 , one embodiment of the present invention is not limited to this. For example, only one circuit 15 may be provided for one imaging device of one embodiment of the present invention.

The pixel 10 is electrically connected to the circuit 12, the circuit 13, and the circuit 14. Furthermore, the pixel 10 is electrically connected to the circuit 13 and the circuit 15 via wiring 55 (VOUT).

The circuit 12 serves as a row driver for selecting a row of the pixel array 11. The circuit 13 serves as a column driver for selecting a column of the pixel array 11. The circuit 14 serves as an A/D conversion circuit.

A variety of circuits, such as a decoder and a shift register, are used for the circuit 12 and the circuit 13.

The circuit 15 has a function of determining whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame in the difference detection mode. This can be performed by comparing the potential of the signal output from the wiring 55 (VOUT) in the difference detection mode with the potential of the signal output from the wiring 55 (VOUT) in the case where the potential of the node FD of the pixel 10 illustrated in FIG. 1 is the potential VR of the wiring 52 (VR).

Note that in the case where the potential of the node FD included in the pixel 10 is the potential VR of the wiring 52 (VR), the potential of the signal output from the wiring 55 (VOUT) is referred to as a reference potential in some cases.

When the potential of the signal output from the wiring 55 (VOUT) in the difference detection mode is different from the reference potential, it can be determined that there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame in the circuit 15. In contrast, when the potential of the signal output from the wiring 55 (VOUT) in the difference detection mode is equal to the reference potential, it can be determined that there is no difference.

The circuit 15 has a function of generating a determination signal 16 after the difference determination. The determination signal 16 can be a 1-bit output and has a function of transferring the results of the difference determination to a circuit and an external device included in the imaging device of one embodiment of the present invention.

In the case where it is determined that there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame, the determination signal 16 is made active. In contrast, in the case where it is determined that there is no difference, the determination signal 16 is made inactive.

Here, “the determination signal 16 is made active” means that, for example, the potential of the determination signal 16 is set at an H level. Moreover, “the determination signal 16 is made inactive” means that, for example, the potential of the determination signal 16 is set at an L level. The logic of the determination signal 16 may be inverted.

Note that in the difference detection mode, the circuit 14 can be made inactive. In the normal imaging mode, the circuit 15 can be made inactive. Thus, the power consumption can be reduced.

FIG. 7 is a circuit diagram illustrating the configuration of the circuit 15 and a connection relationship between the pixel 10 and the circuit 15. The circuit 15 includes a comparator 17 a, a comparator 17 b, an OR circuit 18, a buffer 19, and a transistor 35.

Note that although the transistor 35 is an n-ch transistor in FIG. 7 , the transistor 35 may be a p-ch transistor depending on circumstances or conditions. Any element other than a transistor may be used for the transistor 35 as long as the element has switching characteristics.

In the circuit 15 illustrated in FIG. 7 , an inverting input terminal of the comparator 17 a and a non-inverting input terminal of the comparator 17 b are electrically connected to the wiring 55 (VOUT). An output terminal of the comparator 17 a and an output terminal of the comparator 17 b are electrically connected to an input terminal of the OR circuit 18. An output terminal of the OR circuit 18 is electrically connected to an input terminal of the buffer 19. An output terminal of the buffer 19 is electrically connected to one of a source and a drain of the transistor 35.

A non-inverting input terminal of the comparator 17 a is electrically connected to a wiring 56 (Vref+). An inverting input terminal of the comparator 17 b is electrically connected to a wiring 57 (Vref−). The other of the source and the drain of the transistor 35 is electrically connected to a wiring 58 (EOUT). A gate of the transistor 35 is electrically connected to a wiring 65 (SW1).

Although not illustrated, the wiring 65 (SW1) is electrically connected to the circuit 13 shown in FIG. 6 .

A potential Vref+ is applied to the wiring 56 (Vref+). A potential Vref− is applied to the wiring 57 (Vref−). Note that the potential Vref+ is lower than the reference potential, and the potential Vref− is higher than the reference potential.

In the difference detection mode, the potential VOUT of a signal output from the wiring 55 (VOUT) after the imaging data of the difference detection frame is obtained is applied to the inverting input terminal of the comparator 17 a and the non-inverting input terminal of the comparator 17 b. The comparator 17 a outputs a signal having an H level potential when the potential VOUT is lower than the potential Vref+ and outputs a signal having an L level potential when the potential VOUT is higher than the potential Vref+. The comparator 17 b outputs a signal having an H level potential when the potential VOUT is higher than the potential Vref− and outputs a signal having an L level potential when the potential VOUT is lower than the potential Vref−.

The OR circuit 18 outputs a signal having an H level potential when at least one of the comparators 17 a and 17 b outputs a signal having an H level potential. The OR circuit 18 outputs a signal having an L level potential when both of the comparators 17 a and 17 b output signals having L level signals. That is, the OR circuit 18 has a function of outputting the determination signal 16.

When the relation of the potential VOUT<the potential Vref+ or the potential VOUT>the potential Vref− is satisfied, the circuit 15 outputs the determination signal 16 having the H level potential. That is, it is determined that there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame. When the relation of the potential Vref+<the potential VOUT<the potential Vref− is satisfied, the circuit 15 outputs the determination signal 16 having the L level potential. That is, it is determined that there is no difference between the imaging data of the reference frame and the imaging data of the difference detection frame.

Note that it is preferable to set the potential Vref+ and the potential Vref− in consideration of the offset voltage caused by variations in characteristics of the photoelectric conversion elements 20 a and 20 b.

The buffer 19 corrects the logic value of the determination signal 16 output from the OR circuit 18 in order to avoid misdetection. In order to output the determination signal 16 to the outside, the potential of the wiring 65 (SW1) is set at the H level (or L level if the transistor 35 is a p-ch transistor) and accordingly the transistor 35 is turned on. In this manner, the determination signal 16 can be output to the outside of the circuit 15 via wiring 58 (EOUT).

Note that the circuit 15 does not necessarily include the buffer 19. Furthermore, the circuit 15 does not necessarily include the OR circuit 18.

The electrical connection relation between the wirings 55 (VOUT), 56 (Vref+), and 57 (Vref−) and the input terminals of the comparators 17 a and 17 b can be changed as appropriate. A logic circuit such as a NOR circuit, an AND circuit, or a NAND circuit can be used as the OR circuit 18 as appropriate. With the above structures, for example, the potential of the determination signal 16 can be set at the L level in the case where it is determined that there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame, and the potential of the determination signal 16 can be set at the H level in the case where it is determined that there is no difference therebetween.

Next, the operation of the imaging device of one embodiment of the present invention is described with reference to a flowchart of FIG. 8 .

First, imaging is performed in the normal imaging mode as shown in FIG. 2 or FIG. 4 (S1). In the mode, imaging data is obtained from all the pixels 10. The obtained imaging data are sequentially converted to digital data in the circuit 14 and output to the external device.

Next, determination whether or not to switch to the difference detection mode is made (S2). When switching conditions determined in advance are not satisfied, the steps S1 and S2 are performed again. The switching conditions can be, for example, a lapse of specified time or input of a signal for switching to the difference detection mode.

When the switching conditions are satisfied, the imaging data of the reference frame is obtained in the difference detection mode as shown in FIG. 3 or FIG. 5 (S3). After that, the imaging data of the difference detection frame is obtained, and the imaging data of the difference detection frame is output to the circuit 15 (S4).

Next, the circuit 15 determines whether or not there is a difference between the imaging data of the reference frame and the imaging data of the difference detection frame (S5). The determination can be made by whether the determination signal 16 is active or inactive. In the case where the determination signal 16 is active, it is determined that there is a difference, and in the case where the determination signal 16 is inactive, it is determined that there is no difference.

When there is no difference, the steps S3 to S5 are repeated. In contrast, when there is a difference, switching to the normal imaging mode is performed, and imaging is performed in a manner similar to the step S1. The above is the operation of the imaging device of one embodiment of the present invention.

Note that in the case where it is determined that there is no difference between the imaging data of the reference frame and the imaging data of the difference detection frame in the step S5, as shown in FIG. 9 , determination whether or not to switch to the normal imaging mode may be made (S6). When switching conditions determined in advance are satisfied, switching to the normal imaging mode is performed, and imaging is performed in a manner similar to the step S1. When predetermined switching conditions are not satisfied, the steps S3 to S5 are repeated as in the case shown in FIG. 8 . The switching conditions can be, for example, a lapse of specified time or input of a control signal for switching to the normal imaging mode.

In the imaging device of one embodiment of the present invention, in the difference detection mode, processing that consumes a lot of electric power, such as A/D conversion, is not necessarily performed, and it is acceptable to perform only minimum processing such as generation of the determination signal 16. Thus, power consumption can be reduced as compared with the case where the difference detection mode is not included and imaging data of all frames is output to an external device.

Note that any of the configurations in FIG. 1 , FIG. 6 , and FIG. 7 can be combined with each other as appropriate.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

Embodiment 2

In this embodiment, a modification example of the pixel 10 of the imaging device of one embodiment of the present invention is described with reference to drawings.

The pixel 10 included in the imaging device of one embodiment of the present invention can have a configuration illustrated in FIG. 10 as well as the configuration illustrated in FIG. 1 . The pixel 10 illustrated in FIG. 10 includes a photoelectric conversion element 20, a transistor 36 a, a transistor 36 b, a transistor 37 a, a transistor 37 b, the transistor 32, the transistor 33, the transistor 34, and the capacitor 41. Note that in FIG. 10 , the transistors 36 a, 36 b, 37 a, 37 b, and 32 to 34 are all n-ch transistors.

In the pixel 10 in FIG. 10 , a cathode of the photoelectric conversion element 20 is electrically connected to one of a source and a drain of the transistor 36 a and one of a source and a drain of the transistor 37 a. An anode of the photoelectric conversion element 20 is electrically connected to one of a source and a drain of the transistor 36 b and one of a source and a drain of the transistor 37 b. The other of the source and the drain of the transistor 36 a is electrically connected to the other of the source and the drain of the transistor 37 b, one of a source and a drain of the transistor 32, a gate of the transistor 33, and one terminal of the capacitor 41. One of a source and a drain of the transistor 33 is electrically connected to one of a source and a drain of the transistor 34.

The other of the source and the drain of the transistor 36 b and the other of the source and the drain of the transistor 37 b are electrically connected to a wiring 51 (VPD). The other of the source and the drain of the transistor 32 is electrically connected to the wiring 52 (VR). The other terminal of the capacitor 41 is electrically connected to the wiring 53 (VSS). The other of the source and the drain of the transistor 34 is electrically connected to the wiring 54 (VPI). The other of the source and the drain of the transistor 33 is electrically connected to the wiring 55 (VOUT).

A gate of the transistor 36 a is electrically connected to a wiring 66 a (TX1 a). Agate of the transistor 36 b is electrically connected to a wiring 66 b (TX1 b). A gate of the transistor 37 a is electrically connected to a wiring 67 a (TX2 a). A gate of the transistor 37 b is electrically connected to a wiring 67 b (TX2 b). A gate of the transistor 32 is electrically connected to the wiring 62 (RES). A gate of the transistor 34 is electrically connected to the wiring 64 (SEL).

The wirings 51 (VPD), 52 (VR), 53 (VSS), and 54 (VPI) can serve as power supply lines. In contrast, the wirings 66 a (TX1 a), 66 b (TX1 b), 67 a (TX2 a), 67 b (TX2 b), 62 (RES), and 64 (SEL) can serve as signal lines.

In the above-described structure, a node to which the other of the source and the drain of the transistor 36 a, the other of the source and the drain of the transistor 37 b, the one of the source and the drain of the transistor 32, the gate of the transistor 33, and the one terminal of the capacitor 41 are connected is a node FD.

In the pixel 10 having the configuration illustrated in FIG. 10 , the photoelectric conversion element 20 is a light-receiving element, and has a function of generating current corresponding to the illuminance of light with which the pixel 10 is irradiated. The transistors 36 a, 36 b, 37 a, and 37 b have a function of controlling the accumulation of charge from the photoelectric conversion element 20 to the node FD or controlling the release of charge from the node FD to the photoelectric conversion element 20. Note that the functions of the transistors 32 to 34 are the same as those in the pixel 10 having the configuration illustrated in FIG. 1 .

Imaging data obtained by the pixel 10 is output as a signal via the wiring 55 (VOUT).

When the pixel 10 has the configuration illustrated in FIG. 10 , the number of photoelectric conversion elements per pixel can be smaller than the pixel 10 having the configuration illustrated in FIG. 1 . Thus, in the pixel 10 having the configuration illustrated in FIG. 10 , an occupied area per pixel can be small, and therefore, the definition of the imaging device can be increased.

FIG. 11 , FIG. 12 , FIG. 13 , and FIG. 14 are each a timing chart showing the operation of the pixel 10 illustrated in FIG. 10 . The timing charts show the potentials of the wirings 51 (VPD), 66 a (TXla), 66 b (TXTb), 67 a (TX2 a), 67 b (TX2 b), 62 (RES), and 64 (SEL) and the node FD.

Note that when the pixel 10 is operated on the basis of the timing charts shown in FIG. 11 and FIG. 12 , the potentials of the wirings 52 (VR) and 54 (VPI) are set at the H level, and the potential of the wiring 53 (VSS) is set at the L level.

FIG. 11 is a timing chart showing the operation of the pixel 10 in the normal imaging mode. FIG. 12 is a timing chart showing the operation of the pixel 10 in the difference detection mode.

In the timing charts in FIG. 11 and FIG. 12 , the potentials of the wirings 62 (RES) and 64 (SEL) and the node FD are the same as those shown in FIG. 2 and FIG. 3 at corresponding times. Furthermore, the potentials of the wirings 66 a (TXTa) and 66 b (TXTb) are the same as the potential of the wiring 61 a (TXa) shown in FIG. 2 and FIG. 3 at corresponding times. Moreover, the potentials of the wirings 67 a (TX2 a) and 67 b (TX2 b) are the same as the potential of the wiring 61 b (TXb) shown in FIG. 2 and FIG. 3 at corresponding times.

In the case where the operation in the normal imaging mode is performed as shown in FIG. 11 , the potential of the wiring 51 (VPD) is at the L level. In the case where the operation in the difference detection mode is performed as shown in FIG. 12 , the potential of the wiring 51 (VPD) is set at the H level at Time T110, Time T210, and Time T310 right before Time T111, Time T211, and Time T311, respectively. The potential of the wiring 51 (VPD) is set at the L level at Time T200 and Time T300 right before Time T201 and Time T301, respectively. That is, in the operation in the difference detection mode shown in FIG. 12 , the potential of the wiring 51 (VPD) becomes at the L level when the imaging data of the reference frame is obtained, and becomes at the H level when the imaging data of the difference detection frame is obtained.

The pixel 10 shown in FIG. 10 can also be operated while the potentials of the wirings 53 (VSS) and 54 (VPI) are set at the H level and the potential of the wiring 52 (VR) is set at the L level. The operation of the pixel 10 shown in FIG. 10 in this case is shown in FIG. 13 and FIG. 14 .

FIG. 13 is a timing chart showing the operation of the pixel 10 in the normal imaging mode. FIG. 14 is a timing chart showing the operation of the pixel 10 in the difference detection mode.

In the timing charts in FIG. 13 and FIG. 14 , the potentials of the wirings 62 (RES) and 64 (SEL) and the node FD are the same as those shown in FIG. 4 and FIG. 5 at corresponding times. Furthermore, the potentials of the wirings 66 a (TX1 a) and 66 b (TX1 b) are the same as the potential of the wiring 61 a (TXa) shown in FIG. 4 and FIG. 5 at corresponding times. Moreover, the potentials of the wirings 67 a (TX2 a) and 67 b (TX2 b) are the same as the potential of the wiring 61 b (TXb) shown in FIG. 4 and FIG. 5 at corresponding times.

In the case where the operation in the normal imaging mode is performed as shown in FIG. 13 , the potential of the wiring 51 (VPD) is at the H level. In the case where the operation in the difference detection mode is performed as shown in FIG. 14 , the potential of the wiring 51 (VPD) is set at the L level at Time T110, Time T210, and Time T310 right before Time T111, Time T211, and Time T311, respectively. The potential of the wiring 51 (VPD) is set at the H level at Time T200 and Time T300 right before Time T201 and Time T301, respectively. That is, in the case where the operation in the difference detection mode is performed as shown in FIG. 14 , the potential of the wiring 51 (VPD) becomes at the H level when the imaging data of the reference frame is obtained, and becomes at the L level when the imaging data of the difference detection frame is obtained. The above is the operation of the pixel 10 having the configuration illustrated in FIG. 10 .

Note that as shown in FIG. 11 , FIG. 12 , FIG. 13 , and FIG. 14 , the wirings 66 a (TX1 a) and 66 b (TX1 b) are supplied with potentials at the same level. For example, in the case where the H level potential is applied to the wiring 66 a (TX1 a), the H level potential is applied also to the wiring 66 b (TX1 b), and in the case where the L level potential is applied to the wiring 66 a (TX1 a), the L level potential is applied also to the wiring 66 b (TX1 b). Similarly, the wirings 67 a (TX2 a) and 67 b (TX2 b) are supplied with potentials at the same level. Thus, the wiring 66 a (TX1 a) and the wiring 66 b (TX1 b) in the pixel 10 having the configuration illustrated in FIG. 10 may be the same wiring as illustrated in FIG. 15 . Furthermore, the wirings 67 a (TX2 a) and 67 b (TX2 b) may be the same wiring. With such a configuration, the number of the wirings included in the imaging device of one embodiment of the present invention can be reduced. Thus, the imaging device can be reduced in size.

The pixel 10 may have a configuration illustrated in FIG. 16A. The pixel 10 illustrated in FIG. 16A includes the photoelectric conversion element 20 a, the photoelectric conversion element 20 b, a transistor 31, the transistor 32, the transistor 33, the transistor 34, and the capacitor 41. Note that the transistors 31 to 34 in FIG. 16A are all n-ch transistors.

In the pixel 10 illustrated in FIG. 16A, an anode of the photoelectric conversion element 20 a is electrically connected to an anode of the photoelectric conversion element 20 b. A cathode of the photoelectric conversion element 20 a is electrically connected to one of a source and a drain of the transistor 31. The other of the source and the drain of the transistor 31 is electrically connected to one of a source and a drain of the transistor 32, a gate of the transistor 33, and one terminal of the capacitor 41. One of a source and a drain of the transistor 33 is electrically connected to one of a source and a drain of the transistor 34.

A cathode of the photoelectric conversion element 20 b is electrically connected to the wiring 51 (VPD). The other of the source and the drain of the transistor 32 is electrically connected to the wiring 52 (VR). The other terminal of the capacitor 41 is electrically connected to the wiring 53 (VSS). The other of the source and the drain of the transistor 34 is electrically connected to the wiring 54 (VPI). The other of the source and the drain of the transistor 33 is electrically connected to the wiring 55 (VOUT).

A gate of the transistor 31 is electrically connected to a wiring 61 (TX). A gate of the transistor 32 is electrically connected to the wiring 62 (RES). A gate of the transistor 34 is electrically connected to the wiring 64 (SEL).

The wirings 51 (VPD), 52 (VR), 53 (VSS), and 54 (VPI) can serve as power supply lines. In contrast, the wirings 61 (TX), 62 (RES), and 64 (SEL) can serve as signal lines.

In the above-described structure, a node to which the other of the source and the drain of the transistor 31, the one of the source and the drain of the transistor 32, the gate of the transistor 33, and the one terminal of the capacitor 41 are connected is a node FD.

In the pixel 10 having the configuration illustrated in FIG. 16A, the transistor 31 has a function of controlling the accumulation of charge from the photoelectric conversion elements 20 a and 20 b to the node FD or controlling the release of charge from the node FD to the photoelectric conversion elements 20 a and 20 b. Note that the functions of the photoelectric conversion elements 20 a and 20 b and the transistors 32 to 34 are the same as those in the pixel 10 in FIG. 1 .

Imaging data obtained by the pixel 10 can be output as a signal via the wiring 55 (VOUT).

Note that the pixel 10 may have a configuration illustrated in FIG. 16B. The configuration illustrated in FIG. 16B is different from that in FIG. 16A in that a cathode of the photoelectric conversion element 20 a is electrically connected to a cathode of the photoelectric conversion element 20 b, an anode of the photoelectric conversion element 20 a is electrically connected to one of the source and the drain of the transistor 31, and an anode of the photoelectric conversion element 20 b is electrically connected to the wiring 51 (VPD).

With the pixel 10 having the configuration illustrated in FIG. 16A or 16B, the number of transistors per pixel can be reduced. Thus, an occupied area per pixel can be small, and therefore, the definition of the imaging device can be increased.

FIG. 17 , FIG. 18 , FIG. 19 , and FIG. 20 are each a timing chart showing the operation of the pixel 10 illustrated in FIG. 16A or 16B. The timing charts show the potentials of the wirings 51 (VPD), 61 (TX), 62 (RES), and 64 (SEL) and the node FD.

Note that when the pixel 10 is operated on the basis of the timing charts shown in FIG. 17 and FIG. 18 , the potentials of the wirings 52 (VR) and 54 (VPI) are set at the H level, and the potential of the wiring 53 (VSS) is set at the L level.

FIG. 17 is a timing chart showing the operation of the pixel 10 in the normal imaging mode. FIG. 18 is a timing chart showing the operation of the pixel 10 in the difference detection mode.

In the timing charts in FIG. 17 and FIG. 18 , the potentials of the wirings 62 (RES) and 64 (SEL) and the node FD are the same as those in the timing charts shown in FIG. 2 and FIG. 3 at corresponding times.

In the case where the operation in the normal imaging mode is performed as shown in FIG. 17 , the potential of the wiring 61 (TX) is the same as that of the wiring 61 a (TXa) shown in FIG. 2 at corresponding times. Note that the potential of the wiring 51 (VPD) is at the L level.

In the case where the operation in the difference detection mode is performed as shown in FIG. 18 , the potential of the wiring 61 (TX) is set at the H level at the time when the potential of at least one of the wirings 61 a (TXa) and 61 b (TXb) is at the H level in the timing chart shown in FIG. 3 . In the timing chart shown in FIG. 3 , the potential of the wiring 61 a (TXa) is at the H level in the period from Time T101 to Time T103, the period from Time T201 to Time T203, and the period from Time T301 to Time T303, and the potential of the wiring 61 b (TXb) is at the L level in the period from Time T111 to Time T112, the period from Time T211 to Time T212, and the period from Time T311 to Time T312. Thus, the potential of the wiring 61 (TX) is set at the H level in the period from Time T101 to Time T103, the period from Time T111 to Time T112, the period from Time T201 to Time T203, the period from Time T211 to Time T212, the period from Time T301 to Time T303, and the period from Time T311 to Time T312. The potential of the wiring 61 (TX) is set at the L level in a period other than the above periods.

In the case where the operation in the difference detection mode is performed as shown in FIG. 18 , the potential of the wiring 51 (VPD) is set at the H level at Time T110, Time T210, and Time T310 right before Time T111, Time T211, and Time T311, respectively. The potential of the wiring 51 (VPD) is set at the L level at Time T200 and Time T300 right before Time T201 and Time T301, respectively. That is, in the case where the operation in the difference detection mode is performed shown in FIG. 18 , the potential of the wiring 51 (VPD) becomes at the L level when the imaging data of the reference frame is obtained, and becomes at the H level when the imaging data of the difference detection frame is obtained.

The pixel 10 shown in FIG. 16A or 16B can also be operated while the potentials of the wirings 53 (VSS) and 54 (VPI) are set at the H level and the potential of the wiring 52 (VR) is set at the L level. The operation of the pixel 10 shown in FIG. 16A or 16B in this case is shown in FIG. 19 and FIG. 20 .

FIG. 19 is a timing chart showing the operation of the pixel 10 in the normal imaging mode. FIG. 20 is a timing chart showing the operation of the pixel 10 in the difference detection mode.

In the timing charts in FIG. 19 and FIG. 20 , the potential of the node FD is the same as that in the timing chart shown in FIG. 4 and FIG. 5 at corresponding times. Furthermore, the potentials of the wirings 61 (TX), 62 (RES), and 64 (SEL) are the same as those in the timing charts shown in FIG. 17 and FIG. 18 at corresponding times.

In the case where the operation in the normal imaging mode is performed as shown in FIG. 19 , the potential of the wiring 51 (VPD) is at the H level. In the case where the operation in the difference detection mode is performed as shown in FIG. 20 , the potential of the wiring 51 (VPD) is set at the L level at Time T110, Time T210, and Time T310 right before Time T111, Time T211, and Time T311, respectively. The potential of the wiring 51 (VPD) is set at the H level at Time T200 and Time T300 right before Time T201 and Time T301, respectively. That is, in the case where the operation in the difference detection mode is performed as shown in FIG. 20 , the potential of the wiring 51 (VPD) becomes at the H level when the imaging data of the reference frame is obtained, and becomes at the L level when the imaging data of the difference detection frame is obtained. The above is the operation of the pixel 10 having the configuration illustrated in FIG. 16A or 16B.

FIG. 21 is different from FIG. 1 in that the transistors 31 a, 31 b, and 32 to 34 are all p-ch transistors. When the magnitude relationships of the potentials are reversed as appropriate, for example, FIG. 2 or FIG. 4 can be referred to for the operation in the normal imaging mode, and FIG. 3 or FIG. 5 can be referred to for the operation in the difference detection mode. Note that some of the transistors 31 a, 31 b, and 32 to 34 may be p-ch transistors. Alternatively, a CMOS structure may be employed.

All or some of the transistors 36 a, 36 b, 37 a, and 37 b illustrated in FIG. 10 and FIG. 15 may be p-ch transistors. Alternatively, a CMOS structure may be employed. When the magnitude relationships of the potentials are reversed as appropriate, for example, FIG. 11 or FIG. 13 can be referred to for the operation in the normal imaging mode, and FIG. 12 or FIG. 14 can be referred to for the operation in the difference detection mode.

The transistor 31 illustrated in FIG. 16A or 16B may be a p-ch transistor. Alternatively, a CMOS structure may be employed. When the magnitude relationships of the potentials are reversed as appropriate, for example, FIG. 17 or FIG. 19 can be referred to for the operation in the normal imaging mode, and FIG. 18 or FIG. 20 can be referred to for the operation in the difference detection mode.

Although the transistor 34 lies between the transistor 33 and the wiring 54 (VPI) in FIG. 1 , the transistor 33 may lie between the transistor 34 and the wiring 54 (VPI) as shown in FIG. 22 .

The pixels 10 of the imaging device, which is one embodiment of the present invention, may have a structure in FIG. 23A or 23B.

FIG. 23A illustrates a configuration in which the transistor 32 is excluded from the pixel 10 illustrated in FIG. 1 . In this case, the wiring 51 a (VPDa) is configured to switch between the H level potential and the L level potential. The reset operation of the node FD can be performed by setting the potential of the wiring 51 a (VPDa) at the H level while the transistor 31 a is on. When the potential of the wiring 51 a (VPDa) is set at the H level, a forward bias is applied to the photoelectric conversion element 20 a. Thus, the potential of the node FD can be reset to the H level potential.

Note that in the case where the potential of the node FD is reset to the L level potential, the wiring 51 b (VPDb) may be configured to switch between the H level potential and the L level potential. The reset operation of the node FD can be performed by setting the potential of the wiring 51 b (VPDb) at the L level while the transistor 31 b is on. When the potential of the wiring 51 b (VPDb) is set at the L level, a forward bias is applied to the photoelectric conversion element 20 b. Thus, the potential of the node FD can be reset to the L level potential.

In the case of performing operation for detecting light, the potential of the wiring 51 a (VPDa) is set at the L level if the transistor 31 a is turned on, whereas the potential of the wiring 51 b (VPDb) is set at the H level if the transistor 31 b is turned on. Accordingly, a reverse bias is applied to the photoelectric conversion elements 20 a and 20 b, and thus imaging data corresponding to the illuminance of light can be obtained.

FIG. 23B illustrates a configuration in which the capacitor 41 is excluded from the pixel 10 illustrated in FIG. 1 . In this case, charge is accumulated in the node FD by the gate capacitance of the transistor 33, the parasitic capacitance of a wiring electrically connected to the node FD, and the like.

With the configuration of FIG. 23A or FIG. 23B, an occupied area per pixel in the imaging device of one embodiment of the present invention can be small. Thus, the definition of the imaging device can be increased.

Note that some wirings are not illustrated in FIGS. 23A and 23B.

Although wirings that are supplied with the same potential are illustrated as different wirings in FIG. 1 , one wiring may serve as those wirings. For example, the wiring 51 b (VPDb), the wiring 52 (VR), and the wiring 54 (VPI) that are supplied with the H level potential may be one wiring as illustrated in the pixel 10 in FIG. 24 . Alternatively, as in the pixel 10 illustrated in FIG. 25 , the wiring 51 a (VPDa) and the wiring 53 (VSS) that are supplied with the L level potential may be one wiring.

With the pixel 10 having the configuration illustrated in FIG. 24 and/or the configuration illustrated in FIG. 25 , the number of the wirings included in the imaging device of one embodiment of the present invention can be reduced. Thus, the imaging device can be reduced in size.

The transistors 31 a, 31 b, and 32 to 34 included in the pixel 10 having the configuration illustrated in FIG. 1 may be transistors whose active layers or active regions contain oxide semiconductors (hereinafter referred to as OS transistors).

Unless otherwise specified, the off-state current in this specification refers to a drain current of a transistor in the off state (also referred to as non-conduction state and cutoff state). Unless otherwise specified, the off state of an n-channel transistor means that the voltage V_(gs) between its gate and source (V_(gs): gate-source voltage) is lower than the threshold voltage V_(th), and the off state of a p-channel transistor means that the gate-source voltage V_(gs) is higher than the threshold voltage V_(th). For example, the off-state current of an n-channel transistor sometimes refers to a drain current that flows when the gate-source voltage V_(gs) is lower than the threshold voltage V_(th).

The off-state current of a transistor depends on the voltage V_(gs) in some cases. Thus, the off-state current of a transistor is lower than or equal to I means that there is the voltage V_(gs) with which the off-state current of a transistor becomes lower than or equal to I in some cases. Furthermore, the off-state current of a transistor may refer to the off-state current in an off state at the predetermined voltage V_(gs), the off-state current in an off state at the voltage V_(gs) in a predetermined range, the off-state current in an off state at the voltage V_(gs) with which sufficiently reduced off-state current is obtained, or the like.

As an example, the assumption is made of an n-channel transistor where the threshold voltage V_(th) is 0.5 V and the drain current is 1×10⁻⁹ A at the voltage V_(gs) of 0.5 V, 1×10⁻¹³ A at the voltage V_(gs) of 0.1 V, 1×10⁻¹⁹ A at the voltage V_(gs) of −0.5 V, and 1×10⁻²² A at the voltage V_(gs) of −0.8 V. The drain current of the transistor is 1×10⁻¹⁹ A or lower at the voltage V_(gs) of −0.5 V or at the voltage V_(gs) in the range of −0.8 V to −0.5 V; therefore, it can be said that the off-state current of the transistor is 1×10⁻¹⁹ A or lower. Since there is the voltage V_(gs) at which the drain current of the transistor is 1×10⁻²² A or lower, it may be said that the off-state current of the transistor is 1×10⁻²² A or lower.

In this specification, the off-state current of a transistor with a channel width W is sometimes represented by a current value in relation to the channel width W or by a current value per given channel width (e.g., 1 μm). In the latter case, the off-state current may be expressed in the unit with the dimension of current per length (e.g., A/μm).

The off-state current of a transistor depends on temperature in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at room temperature, 60° C., 85° C., 95° C., or 125° C. Alternatively, the off-state current may be an off-state current at a temperature at which the reliability of a semiconductor device or the like including the transistor is ensured or a temperature at which the semiconductor device or the like is used (e.g., temperature in the range of 5° C. to 35° C.). The description “an off-state current of a transistor is lower than or equal to I” may refer to a situation where there is the voltage V_(gs) at which the off-state current of a transistor is lower than or equal to I at room temperature, 60° C., 85° C., 95° C., 125° C., a temperature at which the reliability of a semiconductor device including the transistor is ensured, or a temperature at which the semiconductor device or the like including the transistor is used (e.g., temperature in the range of 5° C. to 35° C.).

The off-state current of a transistor depends on the voltage V_(ds) between its drain and source in some cases. Unless otherwise specified, the off-state current in this specification may be an off-state current at the voltage V_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V. Alternatively, the off-state current may be an off-state current at the voltage V_(ds) at which the reliability of a semiconductor device or the like including the transistor is ensured or the voltage V_(ds) used in the semiconductor device or the like. The state where the off-state current of a transistor is I or lower may indicate that the off-state current of the transistor at the voltage V_(ds) of 0.1 V, 0.8 V, 1 V, 1.2 V, 1.8 V, 2.5 V, 3 V, 3.3 V, 10 V, 12 V, 16 V, or 20 V, at the voltage V_(ds) at which the reliability of a semiconductor device or the like including the transistor is ensured, or at the voltage V_(ds) used in the semiconductor device or the like including the transistor is I or lower at a certain voltage V_(gs).

In this specification, the term leakage current sometimes expresses the same meaning as off-state current.

In this specification, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is off, for example.

The use of the OS transistor in the pixel 10 can broaden the dynamic range of imaging. In the case where the pixel 10 having the circuit configuration illustrated in FIG. 1 is operated by the steps shown in FIG. 2 or FIG. 3 , the potential of the node FD is lowered when the illuminance of light with which the pixel 10 is irradiated is high. In the case where the pixel 10 having the circuit configuration illustrated in FIG. 1 is operated by the steps shown in FIG. 4 or FIG. 5 , the potential of the node FD is lowered when the illuminance of light with which the pixel 10 is irradiated is low. Since the OS transistor has an extremely low off-state current, a current based on a gate potential can be accurately output even when the potential of the node FD (the gate potential of the transistor 33) is extremely low. Accordingly, it is possible to broaden the detection range of illuminance, i.e., the dynamic range.

A period during which charge can be held in the node FD can be extremely long owing to the low off-state current of the transistor. Therefore, a global shutter system in which imaging data is obtained in all the pixels at the same time can be used without complicated circuit configurations and operating methods.

In a general imaging device where pixels are arranged in a matrix, a rolling shutter system is employed in which an imaging operation 71, a data retention operation 72, and a read operation 73 are performed row by row as illustrated in FIG. 26A. In the case of employing the rolling shutter system, simultaneousness of imaging is lost. Therefore, when a subject moves, an image is distorted. For this reason, it is preferable to employ a global shutter system in which the imaging operation 71 can be performed simultaneously in all the rows and the read operation 73 can be sequentially performed row by row as illustrated in FIG. 26B. By employing the global shutter system, simultaneousness of imaging in all the pixels in the imaging device can be ensured, and an image with little distortion can be easily obtained even when a subject moves.

In addition, the OS transistor has lower temperature dependence of change in electrical characteristics than a transistor whose active layer or active region contains silicon (hereinafter, such a transistor is referred to as a Si transistor), and thus can be used in an extremely wide temperature range. Therefore, an imaging device and a semiconductor device that include OS transistors are suitable for use in automobiles, aircrafts, and spacecrafts.

A transistor connected to the node FD needs to be a transistor with low noise. The channel of a transistor including two or three oxide semiconductor layers to be described later is a buried channel, which has significantly high resistance to noise. Thus, the use of the transistor leads to an image with low noise.

Because OS transistors are used as the transistors 31 a, 31 b, and 32 to 34, the pixel can be composed of OS transistors and a photoelectric conversion element formed using silicon. Such a configuration facilitates an increase in the effective area of the photoelectric conversion element because a Si transistor need not be formed in the pixel. Thus, the photosensitivity can be improved.

Not only the pixel 10 but also peripheral circuits such as the circuits 12 to 15 may include OS transistors. A configuration in which the peripheral circuits are composed only of OS transistors requires no process of forming a Si transistor, and thus is effective in reducing cost of the imaging device. A configuration in which the peripheral circuits are composed only of OS transistors and p-ch Si transistors requires no process of forming an n-ch Si transistor, and thus is effective in reducing cost of the imaging device. Moreover, the peripheral circuits can be CMOS circuits, resulting in lower power consumption of the peripheral circuits, that is, lower power consumption of the imaging device.

In another example, OS transistors are used as the transistors 31 a, 31 b, and 32, and Si transistors are used as the transistors 33 and 34.

The Si transistor has a characteristic of excellent field-effect mobility as compared to the OS transistor. Thus, the amount of current flowing in a transistor functioning as an amplifier transistor or a selection transistor can be increased. For example, in FIG. 1 , the amount of current flowing in the transistors 33 and 34 can be increased depending on charge accumulated in the node FD.

The transistors 36 a, 36 b, 37 a, and 37 b illustrated in FIG. 10 and FIG. 15 and the transistor 31 illustrated in FIGS. 16A and 16B may be OS transistors.

The transistors 31 a, 31 b, and 32 in the pixels 10 illustrated in FIG. 1 may each include a back gate as illustrated in FIGS. 27A and 27B. FIG. 27A illustrates a configuration in which a constant potential is applied to the back gates, which enables control of the threshold voltages. FIG. 27B illustrates a configuration in which the same potential is applied to the back gates and front gates, which enables an increase in on-state current. The transistors 31 a, 31 b, and 32 to 34 may each have a back gate as illustrated in FIGS. 27C and 27D.

Moreover, as illustrated in FIG. 27E, a configuration in which the same potential is applied to a front gate and a back gate and a configuration in which a constant potential is applied to a back gate may be optionally combined as necessary for the transistors in one pixel. Furthermore, a circuit configuration in which a back gate is not provided may be optionally combined with any of the above configurations. As the configuration in which a constant potential is applied to a back gate, for example, a configuration in which the same potential is applied to all the back gates can be employed as illustrated in FIG. 27F, for example.

Note that some wirings are not illustrated in FIGS. 27A to 27F.

The transistors 36 a, 36 b, 37 a, and 37 b illustrated in FIG. 10 and FIG. 15 and the transistor 31 illustrated in FIGS. 16A and 16B may each be provided with a back gate. In each of the transistors, the back gate may be supplied with the same potential as the front gate or a constant potential.

Since an OS transistor has a lower on-state current than a Si transistor, it is particularly preferable that the OS transistor have a back gate. For example, in the case where the transistors 31 a, 31 b, and 32 to 34 are OS transistors, the transistors 31 a, 31 b, and 32 to 34 preferably have back gates. In the case where the transistors 31 a, 31 b, and 32 are OS transistors, for example, the transistors 31 a, 31 b, and 32 preferably have back gates.

Note that the configurations illustrated in FIG. 1 , FIG. 10 , FIG. 15 , FIGS. 16A and 16B, FIG. 21 , FIG. 22 , FIGS. 23A and 23B, FIG. 24 , FIG. 25 , and FIGS. 27A to 27F can be combined with each other as appropriate.

In this embodiment, one embodiment of the present invention has been described. Other embodiments of the present invention are described in the other embodiments. Note that one embodiment of the present invention is not limited to them. That is, since various embodiments of the present invention are disclosed in this embodiment and the other embodiments, one embodiment of the present invention is not limited to a specific embodiment. Although an example in which a channel formation region, a source region, a drain region, or the like of a transistor includes an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention may include, for example, at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, and an organic semiconductor. Alternatively, for example, depending on circumstances or conditions, various transistors or a channel formation region, a source region, a drain region, or the like of a transistor in one embodiment of the present invention does not necessarily include an oxide semiconductor.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

Embodiment 3

In this embodiment, the use of the imaging device of one embodiment of the present invention other than the difference detection is described with reference to the drawings.

The imaging device of one embodiment of the present invention can also be used to adjust the light sensitivity of a pixel. When the light sensitivity of a pixel included in the imaging device of one embodiment of the present invention is high, a dynamic range is narrowed in imaging under high illuminance because of the limitation on the amount of charge accumulated in imaging in some cases. Thus, in imaging under high illuminance, a dynamic range can be widened by lowering the light sensitivity of a pixel.

Moreover, with the above method, long exposure is possible even in imaging under high illuminance.

In this embodiment, as a pixel, the pixel 10 having the configuration illustrated in FIG. 1 can be used. One of the photoelectric conversion elements 20 a and 20 b has lower light sensitivity than the other. For example, the light-receiving area of one of the photoelectric conversion elements 20 a and 20 b is made smaller than that of the other. Alternatively, for example, a photoelectric conversion layer included in one of the photoelectric conversion elements 20 a and 20 b is formed using a material having lower quantum efficiency than a material for a photoelectric conversion layer included in the other.

The operation of the pixel 10 of this embodiment is described in detail with reference to timing charts of FIGS. 28A and 28B. In the timing charts, the potentials of the wirings 61 a (TXa), 61 b (TXb), 62 (RES), and 64 (SEL) and the node FD are illustrated.

Note that in the case where the pixel 10 is operated in accordance with the timing chart shown in FIG. 28A, the photoelectric conversion element 20 b is made to have lower light sensitivity than the photoelectric conversion element 20 a. Furthermore, the potentials of the wirings 51 b (VPDb), 52 (VR), and 54 (VPI) are set at the H level, and the potentials of the wirings 51 a (VPDa) and 53 (VSS) are set at the L level.

In FIG. 28A, imaging data of the first frame is obtained and read in a period from time T01 to time T05, and imaging data of the second frame is obtained and read in a period from time T11 to time T15. The light sensitivity of the pixel 10 in obtaining the imaging data of the second frame is made lower than that in obtaining the imaging data of the first frame.

First, the obtaining and reading of the imaging data of the first frame are described. At Time T01, the potentials of the wirings 61 a (TXa) and 62 (RES) are set at the H level, whereby the transistors 31 a and 32 are turned on. Furthermore, the potentials of the wirings 61 b (TXb) and 64 (SEL) are set at the L level, whereby the transistors 31 b and 34 are turned off. Accordingly, the potential of the node FD is set to the potential VR of the wiring 52 (VR).

At Time T02, the potential of the wiring 62 (RES) is set at the L level, whereby the transistor 32 is turned off. As a result, the potential of the node FD starts to decrease. As the illuminance of light with which the pixel 10 is irradiated becomes higher, the potential of the node FD decreases greatly.

At time T03, the potential of the wiring 61 a (TXa) is set at the L level, whereby the transistor 31 a is turned off. As a result, the potential of the node FD is held. Through the above operation, the imaging data of the first frame is obtained.

At Time T04, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). Note that the signal corresponds to the imaging data obtained in the period from Time T01 to Time T03. Note that the lower the potential of the node FD is, the lower the potential of the signal that is output from the wiring 55 (VOUT) becomes. In other words, the higher the luminance of light with which the pixel 10 is irradiated is, the lower the potential of the signal output from the wiring 55 (VOUT) becomes.

At Time T05, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the first frame is read and output to an external device.

Next, the obtaining and reading of the imaging data of the second frame are described. At Time T11, the potential of the wiring 61 b (TXb) is set at the H level as well as the potentials of the wirings 61 a (TXa) and 62 (RES), whereby the transistors 31 a, 32, and 31 b are turned on. At this time, the potential of the node FD is set to the potential VR of the wiring 52 (VR).

At Time T12, the potential of the wiring 62 (RES) is set at the L level, whereby the transistor 32 is turned off. As a result, the potential of the node FD starts to decrease.

At time T13, the potentials of the wirings 61 a (TXa) and 61 b (TXb) are set at the L level, whereby the transistors 31 a and 31 b are turned off. As a result, the potential of the node FD is held. Through the above operation, the imaging data of the second frame is obtained.

The transistor 31 b is on in a period from Time T12 to Time T13. Thus, a decrease in the potential of the node FD caused by the photoelectric conversion element 20 a is reduced by the photoelectric conversion element 20 b. That is, when the length of the period from Time T02 to Time T03 and the length of the period from Time T12 to Time T13 are the same, T, and in addition, the illuminance of light with which the pixel 10 is irradiated in the period from Time T02 and Time T03 is the same as that in the period from Time T12 and Time T13, the potential of the node FD at Time T13 is higher than that at Time T03. Thus, the dynamic range of the pixel 10 can be widened.

At Time T14, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). Note that the signal corresponds to the imaging data obtained in the period from Time T11 to Time T13.

At Time T15, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the second frame is read. Note that the higher the potential of the node FD is, the higher the potential of the signal that is output from the wiring 55 (VOUT) becomes. Thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T14 to Time T15 becomes higher than that in the period from Time T04 to Time T05.

Note that in this specification, a mode in which imaging is performed using only a photoelectric conversion element having higher light sensitivity for obtainment of the imaging data of the first frame, for example, is referred to as a normal sensitivity mode. Moreover, a mode in which imaging is performed using both photoelectric conversion elements for obtainment of the imaging data of the second frame, for example, is referred to as a low sensitivity mode.

Note that imaging can be performed using only the photoelectric conversion element 20 b, which has lower light sensitivity. In this case, the potential of the wiring 52 (VR) is set at the L level, and the potential of the wiring 53 (VSS) is set at the H level.

In this embodiment, the pixel 10 illustrated in FIG. 1 can be operated even when the light sensitivity of the photoelectric conversion element 20 b is higher than that of the photoelectric conversion element 20 a. The operation of the pixel 10 in this case is described with reference to the timing chart in FIG. 28B.

Note that when the pixel 10 is operated on the basis of the timing charts shown in FIG. 28B, the potentials of the wirings 51 b (VPDb), 53 (VSS), and 54 (VPI) are set at the H level, and the potentials of the wirings 51 a (VPDa) and 52 (VR) are set at the L level.

In FIG. 28B, imaging data of the first frame is obtained and read in a period from time T01 to time T05, and imaging data of the second frame is obtained and read in a period from time T11 to time T15. The light sensitivity of the pixel 10 in obtaining the imaging data of the second frame is made lower than that in obtaining the imaging data of the first frame.

First, the obtaining and reading of the imaging data of the first frame are described. At Time T01, the potentials of the wirings 61 b (TXb) and 62 (RES) are set at the H level, whereby the transistors 31 b and 32 are turned on. Furthermore, the potentials of the wirings 61 a (TXa) and 64 (SEL) are set at the L level, whereby the transistors 31 a and 34 are turned off. Accordingly, the potential of the node FD is set to the potential VR of the wiring 52 (VR).

At Time T02, the potential of the wiring 62 (RES) is set at the L level, whereby the transistor 32 is turned off. As a result, the potential of the node FD starts to increase. As the illuminance of light with which the pixel 10 is irradiated becomes higher, the potential of the node FD rises greatly.

At time T03, the potential of the wiring 61 b (TXb) is set at the L level, whereby the transistor 31 b is turned off. As a result, the potential of the node FD is held. Through the above operation, the imaging data of the first frame is obtained.

At Time T04, the potential of the wiring 64 (SEL) is set at the H level, whereby the transistor 34 is turned on. As a result, a signal in accordance with the potential of the node FD is output from the wiring 55 (VOUT). Note that the signal corresponds to the imaging data obtained in the period from Time T01 to Time T03. Note that the higher the potential of the node FD is, the higher the potential of the signal that is output from the wiring 55 (VOUT) becomes. In other words, the higher the luminance of light with which the pixel 10 is irradiated is, the higher the potential of the signal output from the wiring 55 (VOUT) becomes.

At Time T05, the potential of the wiring 64 (SEL) is set at the L level, whereby the transistor 34 is turned off. Through the above operation, the imaging data of the first frame is read and output to an external device.

Next, the obtaining and reading of the imaging data of the second frame are described. The potentials of the wirings 61 (TXa), 61 b (TXb), 62 (RES), and 64 (SEL) in the period from Time T11 to Time T15 shown in the timing chart of FIG. 28B are the same as those shown in the timing chart of FIG. 28A.

The transistor 31 a is on in the period from Time T12 to Time T13 shown in FIG. 28B. Thus, an increase in the potential of the node FD caused by the photoelectric conversion element 20 b is reduced by the photoelectric conversion element 20 a. That is, when the length of the period from Time T02 to Time T03 and the length of the period from Time T12 to Time T13 are the same, T, and in addition, the illuminance of light with which the pixel 10 is irradiated in the period from Time T02 and Time T03 is the same as that in the period from Time T12 and Time T13, the potential of the node FD at Time T13 is lower than that at Time T03. Thus, the dynamic range of the pixel 10 can be widened.

Note that the lower the potential of the node FD is, the lower the potential of the signal that is output from the wiring 55 (VOUT) becomes; thus, the potential of the signal output from the wiring 55 (VOUT) in the period from Time T14 to Time T15 becomes lower than that in the period from Time T04 to Time T05.

Note that imaging can be performed using only the photoelectric conversion element 20 a, which has lower light sensitivity. In this case, the potential of the wiring 52 (VR) is set at the H level, and the potential of the wiring 53 (VSS) is set at the L level.

Note that in this embodiment, in the case where the pixel 10 is operated in accordance with the timing chart shown in FIG. 28B, the wiring 61 a (TXa) can be electrically connected to the other of the source and the drain of the transistor 31 a as illustrated in FIG. 29A. With such a configuration, the transistor 31 a can be off when the potential of the node FD is low and can be on when the potential of the node FD is high. That is, when the illuminance of light with which the pixel 10 is irradiated is low, the transistor 31 a is off and the pixel 10 is operated in the normal sensitivity mode. In contrast, when the illuminance of light with which the pixel 10 is irradiated is low, the transistor 31 a is on and the pixel 10 is operated in the low sensitivity mode. Thus, without manual control of the potential of the wiring 61 a (TXa), the light sensitivity of the pixel 10 can be automatically adjusted in accordance with the illuminance of light with which the pixel 10 is irradiated.

In the case where the pixel 10 has a configuration illustrated in FIG. 29A, the illuminance of light that is a boundary between the normal sensitivity mode and the low sensitivity mode can be adjusted by adjusting the threshold voltage of the diode-connected transistor 31 a. For example, when the threshold voltage of the transistor 31 a is set higher, the illuminance of light at which the normal sensitivity mode and the low sensitivity mode are switched becomes higher.

FIG. 29B is a modification example of the pixel 10 having the configuration illustrated in FIG. 29A. FIG. 29B is different from FIG. 29A in that a transistor 38 is provided. One of a source and a drain of the transistor 38 is electrically connected to the wiring 61 a (TXa). The other of the source and the drain of the transistor 38 is electrically connected to the other of the source and the drain of the transistor 31 a. A gate of the transistor 38 is electrically connected to a wiring 68 (SW2).

The transistor 38 is preferably an OS transistor but may be a Si transistor. Furthermore, a back gate is preferably provided for the transistor 38 but is not necessarily provided.

Note that although the transistor 38 is an n-ch transistor in FIG. 29B, the transistor 38 may be a p-ch transistor.

When the transistor 38 is on, as in the pixel 10 having the configuration illustrated in FIG. 29A, the potential of the wiring 61 a (TXa) can be controlled in accordance with the illuminance of light with which the pixel 10 is irradiated. That is, the light sensitivity of the pixel 10 can be automatically adjusted in accordance with the illuminance of light with which the pixel 10 is irradiated. In contrast, when the transistor 38 is off, as in the pixel 10 having the configuration illustrated in FIG. 1 , the potential of the wiring 61 a (TXa) can be controlled manually. In this case, the normal sensitivity mode and the low sensitivity mode can be freely switched.

Thus, when the pixel 10 has the configuration illustrated in FIG. 29B, whether the potential of the wiring 61 a (TXa) is controlled automatically or manually can be selected.

Note that in the case where the pixel 10 is operated in accordance with the timing chart shown in FIG. 28A, if the transistor 31 b is a p-ch transistor, the wiring 61 b (TXb) can be electrically connected to the other of the source and the drain of the transistor 31 b. With such a configuration, without manual control of the potential of the wiring 61 b (TXb), the light sensitivity of the pixel 10 can be automatically adjusted in accordance with the illuminance of light with which the pixel 10 is irradiated. The illuminance of light that is a boundary between the normal sensitivity mode and the low sensitivity mode can be adjusted by adjusting the threshold voltage of the diode-connected transistor 31 b.

When the transistor 31 b is a p-ch transistor in the pixel 10 illustrated in FIG. 1 , the transistor 38 can be provided, the one of the source and the drain of the transistor 38 can be electrically connected to the wiring 61 b, and the other of the source and the drain of the transistor 38 can be electrically connected to the other of the source and the drain of the transistor 31 b. With such a configuration, whether the potential of the wiring 61 b (TXb) is controlled automatically or manually can be selected.

Note that the configurations illustrated in FIGS. 29A and 29B can be combined with any of the configurations illustrated in FIG. 1 , FIG. 10 , FIG. 15 , FIGS. 16A and 16B, FIG. 21 , FIG. 22 , FIGS. 23A and 23B, FIG. 24 , FIG. 25 , and FIGS. 27A to 27F as appropriate.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

Embodiment 4

In this embodiment, specific structure examples of the imaging device of one embodiment of the present invention are described below with reference to drawings.

FIG. 30A illustrates an example of a cross-sectional view of the imaging device of one embodiment of the present invention and illustrates a specific connection between the photoelectric conversion element 20 a, the photoelectric conversion element 20 b, the transistor 31 a, and the transistor 31 b that are included in each of the pixels 10 in FIG. 1 . Note that the transistors 32 to 34 are not illustrated in FIG. 30A. The imaging device includes a tier 1100 including the transistors 31 a, 31 b, and 32 to 34 and a tier 1200 including the photoelectric conversion elements 20 a and 20 b.

Although the wirings, electrodes, and conductors 91 are illustrated as independent components in cross-sectional views in this embodiment, some of them are provided as one component in some cases when they are electrically connected to each other. In addition, a structure in which a gate, a source, or a drain of the transistor is connected to the wirings through a conductor 91 is only an example. The gate, the source, and the drain of the transistor might each function as a wiring.

Over the components, an insulating layer 92, an insulating layer 93, and the like that can function as protective films, interlayer insulating layers, or planarization films are provided. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as each of the insulating layers 92 and 93 and the like. Alternatively, an organic insulating film such as an acrylic resin film or a polyimide resin film may be used. Top surfaces of the insulating layers 92 and 93 and the like are preferably planarized by chemical mechanical polishing (CMP) or the like as necessary.

In some cases, one or more of the wirings and the like illustrated in the drawing are not provided or a wiring, a transistor, or the like that is not illustrated in the drawing is included in each layer. In some cases, a layer that is not illustrated in the drawing is included in the stacked-layer structure. One or more of the layers illustrated in the drawing are not included in some cases.

Note that although each transistor includes a back gate in FIG. 30A, each transistor does not necessarily include a back gate as illustrated in FIG. 30B. The back gate might be electrically connected to the transistor's front gate that faces the back gate. Note that different fixed potentials might be supplied to the back gate and the front gate. The presence or absence of the back gate can also be applied to another imaging device described in this embodiment.

Any of a variety of elements can be used as the photoelectric conversion elements 20 a and 20 b provided in the tier 1200. FIG. 30A illustrates the photoelectric conversion elements 20 a and 20 b containing a selenium-based material in a photoelectric conversion layer 21. The photoelectric conversion elements 20 a and 20 b containing a selenium-based material have high external quantum efficiency with respect to visible light. Such photoelectric conversion elements can be a highly sensitive sensor in which the amount of amplification of electrons with respect to the amount of incident light is large because of an avalanche phenomenon. Furthermore, the selenium-based material has a high light-absorption coefficient, making the photoelectric conversion layer 21 thin easily.

Amorphous selenium or crystalline selenium can be used as the selenium-based material. Crystalline selenium can be obtained by, for example, depositing amorphous selenium and then performing heat treatment. When the crystal grain size of crystalline selenium is smaller than a pixel pitch, variations in characteristics between pixels can be reduced. Moreover, crystalline selenium has higher spectral sensitivity to visible light and a higher absorption coefficient for visible light than amorphous selenium.

The photoelectric conversion layer 21 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, a layer containing a compound of copper, indium, gallium, and selenium (CIGS) may be used. With the CIS or CIGS, a photoelectric conversion element that can utilize an avalanche phenomenon as in the case of using a single layer of selenium can be formed.

In the photoelectric conversion elements 20 a and 20 b containing the selenium-based material, for example, the photoelectric conversion layer 21 can be provided between a light-transmitting conductive layer 22 and an electrode 26 formed using a metal material or the like. Since CIS and CIGS are p-type semiconductors, an n-type semiconductor such as cadmium sulfide or zinc sulfide may be provided in contact with the p-type semiconductor in order to form a junction.

It is preferable to apply a relatively high voltage (e.g., 10 V or higher) to the photoelectric conversion element in order to cause the avalanche phenomenon. Since the OS transistor has higher drain breakdown voltage than the Si transistor, the application of a relatively high voltage to the photoelectric conversion element is easy. Thus, the combination of the OS transistor having high drain breakdown voltage and the photoelectric conversion element containing the selenium-based material in the photoelectric conversion layer can provide a highly sensitive and highly reliable imaging device.

Although the light-transmitting conductive layer 22 and a wiring 94 are connected to each other through a wiring 95 and the conductor 91 in FIG. 30A, the light-transmitting conductive layer 22 and the wiring 94 may be in direct contact with each other as in FIG. 30C.

The electrode 26, the wiring 94, and the like may each be a multilayer. For example, as illustrated in FIG. 31A, the electrode 26 can include two conductive layers 26 a and 26 b and the wiring 94 can include two conductive layers 94 a and 94 b. In the structure in FIG. 31A, for example, the conductive layers 26 a and 94 a may be made of a low-resistance metal or the like, and the conductive layer 26 b may be made of a metal or the like that exhibits an excellent contact property with the photoelectric conversion layer 21. Such a structure can improve the electrical characteristics of the photoelectric conversion element. Furthermore, even when the conductive layer 94 a contains a metal that causes electrolytic corrosion by being in contact with the light-transmitting conductive layer 22, the electrolytic corrosion can be prevented because the conductive layer 94 b is between the conductive layer 94 a and the light-transmitting conductive layer 22.

The conductive layers 26 a and 94 a can be formed using, for example, aluminum, titanium, or a stack of titanium, aluminum, and titanium that are layered in this order. The conductive layers 26 b and 94 b can be formed using, for example, molybdenum, tungsten, or the like.

The insulating layer 92 and the like may each be a multilayer. In the case where the insulating layer 92 includes insulating layers 92 a and 92 b that have different etching rates as illustrated in FIG. 31B, for example, the conductor 91 has a difference in level. In the case where another insulating layer used as an interlayer insulating layer or a planarization film is a multilayer, the conductor 91 also has a difference in level. Although the insulating layer 92 is formed using two layers here, the insulating layer 92 and another insulating layer may each be formed using three or more layers.

As the photoelectric conversion elements 20 a and 20 b, a PIN diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used.

FIG. 32 illustrates an example in which a thin film PIN photodiode is used as the photoelectric conversion elements 20 a and 20 b. In the photodiode, a p-type semiconductor layer 25, an i-type semiconductor layer 24, and an n-type semiconductor layer 23 are stacked in this order. The i-type semiconductor layer 24 is preferably formed using amorphous silicon. The n-type semiconductor layer 23 and the p-type semiconductor layer 25 can each be formed using amorphous silicon, microcrystalline silicon, or the like that includes a dopant imparting the corresponding conductivity type. A photodiode in which a photoelectric conversion layer is formed using amorphous silicon has high sensitivity in a visible light wavelength region, and thus can easily sense weak visible light.

In the photoelectric conversion elements 20 a and 20 b illustrated in FIG. 32 , the p-type semiconductor layer 25 is electrically connected to the electrode 26. Furthermore, the n-type semiconductor layer 23 is electrically connected to the wiring 94 through the conductor 91 and the wiring 95.

FIGS. 33A to 33F show other examples of the structure of the photoelectric conversion elements 20 a and 20 b having a configuration of a PIN thin film photodiode and the connection between the wirings and the photoelectric conversion elements 20 a and 20 b. Note that the structure of the photoelectric conversion elements 20 a and 20 b and the connection between the wirings and the photoelectric conversion elements 20 a and 20 b are not limited thereto, and other configurations may be applied.

FIG. 33A illustrates a structure of the photoelectric conversion elements 20 a and 20 b that includes the light-transmitting conductive layer 22 in contact with the n-type semiconductor layer 23. The light-transmitting conductive layer 22 serves as an electrode and can increase the output current of the photoelectric conversion elements 20 a and 20 b.

For the light-transmitting conductive layer 22, the following can be used: indium tin oxide; indium tin oxide containing silicon; indium oxide containing zinc; zinc oxide; zinc oxide containing gallium; zinc oxide containing aluminum; tin oxide; tin oxide containing fluorine; tin oxide containing antimony; graphene; or the like. The light-transmitting conductive layer 22 is not limited to a single layer, and may be a stacked layer of different films.

FIG. 33B illustrates a structure in which the n-type semiconductor layer 23 of the photoelectric conversion elements 20 a and 20 b is directly connected to the wiring 95.

FIG. 33C illustrates a structure of the photoelectric conversion elements 20 a and 20 b in which the light-transmitting conductive layer 22 is in contact with the n-type semiconductor layer 23 and the wiring 95 is electrically connected to the light-transmitting conductive layer 22.

FIG. 33D illustrates a structure in which an opening exposing the n-type semiconductor layer 23 is provided in an insulating layer covering the photoelectric conversion elements 20 a and 20 b, and the light-transmitting conductive layer 22 that covers the opening is electrically connected to the wiring 95.

FIG. 33E illustrates a structure including the conductor 91 that penetrates the photoelectric conversion elements 20 a and 20 b. In the structure, the wiring 94 is electrically connected to the n-type semiconductor layer 23 through the conductor 91. Note that in the drawing, the wiring 94 appears to be electrically connected to the electrode 26 through the p-type semiconductor layer 25. However, because of a high electric resistance in the lateral direction of the p-type semiconductor layer 25, the resistance between the wiring 94 and the electrode 26 is extremely high when there is an appropriate distance therebetween. Thus, the photoelectric conversion elements 20 a and 20 b have diode characteristics without a short circuit between the anode and the cathode. Note that two or more conductors 91 that are electrically connected to the n-type semiconductor layer 23 may be provided.

FIG. 33F illustrates a structure in which the photoelectric conversion elements 20 a and 20 b in FIG. 33E is provided with the light-transmitting conductive layer 22 in contact with the n-type semiconductor layer 23.

Note that each of the photoelectric conversion elements 20 a and 20 b illustrated in FIGS. 33D to 33F has an advantage of having a large light-receiving area because wirings and the like do not overlap with a light-receiving region.

Alternatively, as illustrated in FIG. 34 , the photoelectric conversion elements 20 a and 20 b may be a photodiode including a silicon substrate 100 as a photoelectric conversion layer.

The photoelectric conversion elements 20 a and 20 b formed using the aforementioned selenium-based material, amorphous silicon, or the like can be formed through general semiconductor manufacturing processes such as a deposition process, a lithography process, and an etching process. Therefore, the imaging device of one embodiment of the present invention can be manufactured with a high yield at low cost. In contrast, a photodiode including the silicon substrate 100 as the photoelectric conversion layer requires difficult processes such as a polishing process and a bonding process.

Furthermore, the imaging device of one embodiment of the present invention may have a multilayer structure including a silicon substrate 106 in which a circuit is formed. For example, as illustrated in FIG. 35A, the pixel circuit may overlap with a tier 1400 that includes a transistor 101 and a transistor 102 whose active regions are formed in the silicon substrate 106. FIG. 35B is a cross-sectional view illustrating the transistors in the channel width direction.

The circuit formed in the silicon substrate 106 can have a function of reading a signal that is output from the pixel circuit and converting the signal, for example. The circuit may include, for example, a CMOS inverter as illustrated in the circuit diagram in FIG. 35C. A gate of the transistor 101 (n-ch transistor) is electrically connected to a gate of the transistor 102 (p-ch transistor). One of a source and a drain of one of the transistors 101 and 102 is electrically connected to one of a source and a drain of the other transistor. The other of the source and the drain of the one transistor and the other of the source and the drain of the other transistor are electrically connected to different wirings.

Each of the silicon substrate 100 illustrated in FIG. 34 and the silicon substrate 106 illustrated in FIG. 35A is not limited to a bulk silicon substrate and can be a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor.

Here, as illustrated in FIG. 34 and FIG. 35A, an insulating layer 96 is provided between a region including an oxide semiconductor transistor and a region including a Si device (a Si transistor or a Si photodiode).

Dangling bonds of silicon are terminated with hydrogen in insulating layers provided in the vicinities of the active regions of the transistors 101 and 102. Therefore, the hydrogen has an effect of improving the reliability of the transistors 101 and 102. Meanwhile, hydrogen in insulating layers provided in the vicinity of the oxide semiconductor layer that is the active layer of the transistor 31 a or the like causes generation of carriers in the oxide semiconductor layer, and thus may reduce the reliability of the transistor 31 a or the like. For this reason, the insulating layer 96 that has a function of preventing diffusion of hydrogen is preferably provided between one layer including the Si transistor and another layer stacked thereover that includes the OS transistor. Hydrogen is confined in the one layer by the insulating layer 96, so that the reliability of the transistors 101 and 102 can be improved. Furthermore, diffusion of hydrogen from the one layer to the other layer is inhibited, leading to an improvement in the reliability of the transistor 31 a, which is an OS transistor, or the like.

The insulating layer 96 can be formed using, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or yttria-stabilized zirconia (YSZ).

Note that as illustrated in FIG. 35A, a circuit (e.g., a driver circuit) formed in the silicon substrate 106, the transistor 31 a or the like, and the photoelectric conversion element 20 a or the like can overlap with each other; thus, the integration degree of pixels can be increased. In other words, the resolution of the imaging device can be increased. Such a structure is suitable for an imaging device with, for example, 4K2K, 8K4K, or 16K8K pixels. Note that since the 8K4K imaging device includes thirty-three million pixels, it can also be referred to as “33M.” Furthermore, for example, a structure may be employed in which Si transistors are formed as the transistors 33 and 34 included in the pixel 10 and there is a region where the transistors 33 and 34 overlap with the transistors 31 a, 31 b, and 32 and the photoelectric conversion elements 20 a and 20 b. In that case, the transistors 31 a, 31 b, and 32 are OS transistors.

In the imaging device in FIG. 35A, the photoelectric conversion elements 20 a and 20 b are not provided on the silicon substrate 106. Therefore, optical paths for the photoelectric conversion elements 20 a and 20 b can be ensured without being influenced by the transistors or wirings, and a pixel with a high aperture ratio can be formed.

Although FIGS. 35A and 35B show fin type Si transistors, planar type transistors may be used as illustrated in FIG. 36A. Alternatively, as illustrated in FIG. 36B, transistors each including an active layer 105 formed using a silicon thin film may be used. The active layer 105 can be formed using polycrystalline silicon or single crystal silicon of a silicon-on-insulator (SOI) structure.

The imaging device of one embodiment of the present invention can also have a structure in FIG. 37 .

An imaging device in FIG. 37 is a modification example of the imaging device in FIG. 35A. A CMOS inverter is formed using an OS transistor and a Si transistor.

Here, the transistor 102 provided in the tier 1400 is a p-ch Si transistor, and the transistor 101 provided in the tier 1100 is an n-ch OS transistor. When only the p-ch transistor is provided in the silicon substrate 106, a step of forming a well, an n-type impurity layer, or the like can be omitted.

Although selenium or the like is used for the photoelectric conversion elements 20 a and 20 b in the imaging device in FIG. 37 , a thin film PIN photodiode may be used as in FIG. 32 .

In the imaging device in FIG. 37 , the transistor 101 can be formed through the same process as the transistors 31 a, 31 b, and 32 formed in the tier 1100. Thus, the manufacturing process of the imaging device can be simplified.

As illustrated in FIG. 38 , the imaging device of one embodiment of the present invention may have a structure where a pixel and the silicon substrate 106 in which a circuit is formed are attached to each other. Note that the pixel includes a photodiode formed in the silicon substrate 100 and OS transistors formed over the photodiode. Such a structure facilitates an increase in the effective area of the photodiode formed in the silicon substrate 100. Furthermore, when the integration degree of the circuit formed in the silicon substrate 106 is improved using miniaturized Si transistors, a high-performance semiconductor device can be provided.

FIG. 39A is a cross-sectional view of an example of a mode in which a color filter and the like are added to the imaging device. The cross-sectional view illustrates part of a region including pixel circuits of three pixels. An insulating layer 2500 is formed over the tier 1200 where the photoelectric conversion elements 20 a and 20 b are formed. As the insulating layer 2500, a silicon oxide film or the like with a high visible-light transmitting property can be used. A silicon nitride film may be stacked as a passivation film. Furthermore, a dielectric film of hafnium oxide or the like may be stacked as an anti-reflection film.

A light-blocking layer 2510 may be formed over the insulating layer 2500. The light-blocking layer 2510 has a function of inhibiting color mixing of light passing through the color filter. The light-blocking layer 2510 can be formed using a metal layer of aluminum, tungsten, or the like, or a stack including the metal layer and a dielectric film that functions as an anti-reflection film.

A resin layer 2520 can be formed as a planarization film over the insulating layer 2500 and the light-blocking layer 2510. A color filter 2530 (a color filter 2530 a, a color filter 2530 b, or a color filter 2530 c) is formed in each pixel. For example, the color filter 2530 a, the color filter 2530 b, and the color filter 2530 c each have a color of red (R), green (G), blue (B), yellow (Y), cyan (C), magenta (M), or the like, so that a color image can be obtained.

A light-transmitting insulating layer 2560 or the like can be provided over the color filter 2530.

As illustrated in FIG. 39B, an optical conversion layer 2550 may be used instead of the color filter 2530. Such a structure enables the imaging device to take images in various wavelength regions.

For example, when a filter that blocks light having a wavelength shorter than or equal to that of visible light is used as the optical conversion layer 2550, an infrared imaging device can be obtained. When a filter that blocks light having a wavelength shorter than or equal to that of near infrared light is used as the optical conversion layer 2550, a far infrared imaging device can be obtained. When a filter that blocks light having a wavelength longer than or equal to that of visible light is used as the optical conversion layer 2550, an ultraviolet imaging device can be obtained.

When a scintillator is used for the optical conversion layer 2550, an imaging device that takes an image visualizing the intensity of radiation, which is used for an X-ray imaging device or the like, can be obtained. Radiation such as X-rays that passes through a subject to enter a scintillator is converted into light (fluorescence) such as visible light or ultraviolet light owing to a phenomenon known as photoluminescence. Then, the photoelectric conversion elements 20 a and 20 b detect the light to obtain imaging data. Furthermore, the imaging device having the structure may be used in a radiation detector or the like.

A scintillator is formed using a substance that, when irradiated with radiation such as X-rays or gamma-rays, absorbs energy of the radiation to emit visible light or ultraviolet light, or a material containing the substance. Materials such as Gd₂O₂S:Tb, Gd₂O₂S:Pr, Gd₂O₂S:Eu, BaFCl:Eu, NaI, CsI, CaF₂, BaF₂, CeF₃, LiF, LiI, and ZnO and a resin or ceramics in which any of the materials is dispersed are known, for example.

In the photoelectric conversion elements 20 a and 20 b containing a selenium-based material, radiation such as X-rays can be directly converted into charge; thus, the scintillator is unnecessary.

As illustrated in FIG. 39C, a microlens array 2540 may be provided over the color filters 2530 a, 2530 b, and 2530 c. Light transmitting lenses included in the microlens array 2540 passes through the color filters positioned thereunder and enters the photoelectric conversion elements 20 a and 20 b. Note that a region other than the tier 1200 in FIGS. 39A to 39C is referred to as a layer 1600.

Note that in FIGS. 39A to 39C, the photoelectric conversion element 20 b is not illustrated.

The specific structure of the imaging device in FIG. 39C is illustrated in FIG. 40 by taking an example of the imaging device in FIG. 30A. In addition, the specific structure of the imaging device in FIG. 39C is illustrated in FIG. 41 by taking an example of the imaging device in FIG. 34 .

The imaging device of one embodiment of the present invention may be combined with a diffraction grating 1500 as illustrated in FIG. 42 and FIG. 43 . An image of a subject through the diffraction grating 1500 (i.e., a diffraction pattern) can be scanned into a pixel, and an input image (a subject image) can be formed from an obtained image in the pixel by arithmetic processing. In addition, the use of the diffraction grating 1500 instead of a lens can reduce the cost of the imaging device.

The diffraction grating 1500 can be formed using a light-transmitting material. For example, an inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used. Alternatively, an organic insulating film such as an acrylic resin film or a polyimide resin film may be used. Further alternatively, a stack including the inorganic insulating film and the organic insulating film may be used.

The diffraction grating 1500 can be formed by a lithography process using a photosensitive resin or the like. Alternatively, the diffraction grating 1500 can be formed by a lithography process and an etching process. Further alternatively, the diffraction grating 1500 can be formed by nanoimprint lithography, laser scribing, or the like.

Note that a space X may be provided between the diffraction grating 1500 and the microlens array 2540. The space X can be less than or equal to 1 mm, and preferably less than or equal to 100 μm. The space may be an empty space or may be a sealing layer or an adhesion layer formed using a light-transmitting material. For example, an inert gas such as nitrogen or a rare gas can be sealed in the space. Alternatively, an acrylic resin, an epoxy resin, a polyimide resin, or the like may be provided in the space. Further alternatively, a liquid such as silicone oil may be provided. Even in the case where the microlens array 2540 is not provided, the space X may be provided between the color filter 2530 and the diffraction grating 1500.

As illustrated in FIG. 44A1 and FIG. 44B1, the imaging device of one embodiment of the present invention may be bent. FIG. 44A1 illustrates a state in which the imaging device is bent in the direction of dashed-two dotted line X1-X2. FIG. 44A2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2 in FIG. 44A1. FIG. 44A3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2 in FIG. 44A1.

FIG. 44B1 illustrates a state where the imaging device is bent in the direction of dashed-two dotted line X3-X4 and the direction of dashed-two dotted line Y3-Y4. FIG. 44B2 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4 in FIG. 44B1. FIG. 44B3 is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4 in FIG. 44B1.

Bending the imaging device can reduce field curvature and astigmatism. Thus, the optical design of a lens or the like, which is used in combination of the imaging device, can be facilitated. For example, the number of lenses used for aberration correction can be reduced; accordingly, the size or weight of semiconductor device or the like including the imaging device can be easily reduced. In addition, the quality of an obtained image can be improved.

Note that the description in this embodiment can be applied to the pixels 10 having any of the configurations in this specification, including the pixels 10 having the configurations illustrated in FIG. 10 , FIG. 15 , FIGS. 16A and 16B and FIGS. 29A and 29B.

This embodiment can be implemented in combination with any of the structures described in the other embodiments as appropriate.

Embodiment 5

In this embodiment, a transistor containing an oxide semiconductor that can be used in one embodiment of the present invention is described with reference to drawings. In the drawings in this embodiment, some components are enlarged, reduced in size, or omitted for easy understanding.

FIG. 45A is a top view illustrating a transistor 401 in one embodiment of the present invention. A cross section in the direction of dashed-dotted line B1-B2 in FIG. 45A is illustrated in FIG. 45B. A cross section in the direction of dashed-dotted line B3-B4 in FIG. 45A is illustrated in FIG. 47A. Note that the direction of dashed-dotted line B1-B2 is referred to as a channel length direction, and the direction of dashed-dotted line B3-B4 is referred to as a channel width direction, in some cases.

The transistor 401 includes a substrate 415, an insulating layer 420, an oxide semiconductor layer 430, a conductive layer 440, a conductive layer 450, an insulating layer 460, a conductive layer 470, an insulating layer 475, and an insulating layer 480.

The insulating layer 420 is in contact with the substrate 415. The oxide semiconductor layer 430 is in contact with the insulating layer 420. The conductive layer 440 and the conductive layer 450 are in contact with the insulating layer 420 and the oxide semiconductor layer 430. The insulating layer 460 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 440, and the conductive layer 450. The conductive layer 470 is in contact with the insulating layer 460. The insulating layer 475 is in contact with the insulating layer 420, the conductive layer 440, the conductive layer 450, and the conductive layer 470. The insulating layer 480 is in contact with the insulating layer 475.

Here, in the oxide semiconductor layer 430, a region in contact with the conductive layer 440, a region in contact with the conductive layer 450, and a region in contact with the insulating layer 460 are referred to as a region 531, a region 532, and a region 533, respectively.

Furthermore, the conductive layers 440 and 450 are electrically connected to the oxide semiconductor layer 430.

The conductive layer 440 can function as one of a source and a drain. The conductive layer 450 functions as the other of the source and the drain. The insulating layer 460 functions as a gate insulating layer. The conductive layer 470 functions as a gate.

The region 531, the region 532, and the region 533 that are illustrated in FIG. 45B functions as one of a source region and a drain region, the other of the source region and the drain region, and a channel formation region, respectively.

Each of the conductive layers 440 and 450 is a single layer in the drawing, but also may be a stack of two or more layers. The conductive layer 470 includes two layers, a conductive layer 471 and a conductive layer 472, in the drawing, but also may be a single layer or a stack of three or more layers. The same applies to other transistors described in this embodiment.

The insulating layer 480 may function as a planarization film as necessary.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 45C and 45D. FIG. 45C is a top view of a transistor 402. A cross section in the direction of dashed-dotted line C1-C2 in FIG. 45C is illustrated in FIG. 45D. A cross section in the direction of dashed-dotted line C3-C4 in FIG. 45C is illustrated in FIG. 47B. The direction of dashed-dotted line C1-C2 is referred to as a channel length direction, and the direction of dashed-dotted line C3-C4 is referred to as a channel width direction in some cases.

The transistor 402 is different from the transistor 401 in that an end portion of the insulating layer 460 is not aligned with an end portion of the conductive layer 470. In the transistor 402, wide areas of the conductive layers 440 and 450 are covered with the insulating layer 460 and accordingly the electric resistance between the conductive layer 470 and the conductive layers 440 and 450 is high; therefore, the transistor 402 has a feature of a low gate leakage current.

The transistors 401 and 402 each have a top-gate structure including regions where the conductive layer 470 overlaps with the conductive layers 440 and 450. To reduce parasitic capacitance, the width of each of the regions in the channel length direction is preferably greater than or equal to 3 nm and less than 300 nm. Since an offset region is not formed in the oxide semiconductor layer 430 in this structure, a transistor with a high on-state current can be easily formed.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 45E and 45F. FIG. 45E is a top view of a transistor 403. A cross section in the direction of dashed-dotted line D1-D2 in FIG. 45E is illustrated in FIG. 45F. A cross section in the direction of dashed-dotted line D3-D4 in FIG. 45E is illustrated in FIG. 47A. The direction of dashed-dotted line D1-D2 is referred to as a channel length direction, and the direction of dashed-dotted line D3-D4 is referred to as a channel width direction.

In the transistor 403, the insulating layer 420 is in contact with the substrate 415; the oxide semiconductor layer 430 is in contact with the insulating layer 420; the insulating layer 460 is in contact with the insulating layer 420 and the oxide semiconductor layer 430; the conductive layer 470 is in contact with the insulating layer 460; the insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, and the conductive layer 470; the insulating layer 480 is in contact with the insulating layer 475; and the conductive layer 440 and the conductive layer 450 are in contact with the oxide semiconductor layer 430 and the insulating layer 480.

Openings are formed in the insulating layers 475 and 480, and the conductive layers 440 and 450 are electrically connected to the oxide semiconductor layer 430 through the openings.

The transistor 403 may further include, for example, an insulating layer (planarization film) in contact with the conductive layers 440 and 450 and the insulating layer 480 as necessary.

In the oxide semiconductor layer 430, a region that is in contact with the insulating layer 475 and is sandwiched between the region 531 and the region 533 is referred to as a region 534, and a region that is in contact with the insulating layer 475 and is sandwiched between the region 532 and the region 533 is referred to as a region 535.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 46A and 46B. FIG. 46A is a top view of a transistor 404. A cross section in the direction of dashed-dotted line E1-E2 in FIG. 46A is illustrated in FIG. 46B. A cross section in the direction of dashed-dotted line E3-E4 in FIG. 46A is illustrated in FIG. 47A. The direction of dashed-dotted line E1-E2 is referred to as a channel length direction, and the direction of dashed-dotted line E3-E4 is referred to as a channel width direction in some cases.

In the transistor 404, the insulating layer 420 is in contact with the substrate 415; the oxide semiconductor layer 430 is in contact with the insulating layer 420; the conductive layers 440 and 450 are in contact with the insulating layer 420 and the oxide semiconductor layer 430; the insulating layer 460 is in contact with the insulating layer 420 and the oxide semiconductor layer 430; the conductive layer 470 is in contact with the insulating layer 460; the insulating layer 475 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 440, the conductive layer 450, and the conductive layer 470; and the insulating layer 480 is in contact with the insulating layer 475.

The transistor 404 is different from the transistor 403 in that the conductive layers 440 and 450 in contact with the oxide semiconductor layer 430 cover end portions of the oxide semiconductor layer 430.

The transistors 403 and 404 each have a self-aligned structure that does not include regions where the conductive layer 470 overlaps with the conductive layers 440 and 450. A transistor with a self-aligned structure, which has extremely low parasitic capacitance between a gate and a source and between the gate and a drain, is suitable for applications that require high-speed operation.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 46C and 46D. FIG. 46C is a top view of a transistor 405. A cross section in the direction of dashed-dotted line F1-F2 in FIG. 46C is illustrated in FIG. 46D. A cross section in the direction of dashed-dotted line F3-F4 in FIG. 46C is illustrated in FIG. 47A. The direction of dashed-dotted line F1-F2 is referred to as a channel length direction, and the direction of dashed-dotted line F3-F4 is referred to as a channel width direction in some cases.

In the transistor 405, the conductive layer 440 includes two layers, a conductive layer 441 and a conductive layer 442, and the conductive layer 450 includes two layers, a conductive layer 451 and a conductive layer 452. The insulating layer 420 is in contact with the substrate 415. The oxide semiconductor layer 430 is in contact with the insulating layer 420. The conductive layer 441 and the conductive layer 451 are in contact with the oxide semiconductor layer 430. The insulating layer 460 is in contact with the insulating layer 420, the oxide semiconductor layer 430, the conductive layer 441, and the conductive layer 451. The conductive layer 470 is in contact with the insulating layer 460. The insulating layer 475 is in contact with the insulating layer 420, the conductive layer 441, the conductive layer 451, and the conductive layer 470. The insulating layer 480 is in contact with the insulating layer 475. The conductive layer 442 is in contact with the conductive layer 441 and the insulating layer 480. The conductive layer 452 is in contact with the conductive layer 451 and the insulating layer 480.

The conductive layers 441 and 451 are in contact with the top surface of the oxide semiconductor layer 430 and are not in contact with a side surface of the oxide semiconductor layer 430.

The transistor 405 may further include, for example, an insulating layer in contact with the conductive layers 442 and 452 and the insulating layer 480 as necessary.

The conductive layer 441 and the conductive layer 451 are electrically connected to the oxide semiconductor layer 430. Furthermore, the conductive layer 442 is electrically connected to the conductive layer 441, and the conductive layer 452 is electrically connected to the conductive layer 451.

In the oxide semiconductor layer 430, a region overlapping with the conductive layer 441 is the region 531 that can function as one of a source region and a drain region, and a region overlapping with the conductive layer 451 is the region 532 that can function as the other of the source region and the drain region.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 46E and 46F. FIG. 46E is a top view of a transistor 406. A cross section in the direction of dashed-dotted line G1-G2 in FIG. 46E is illustrated in FIG. 46F. A cross section in the direction of dashed-dotted line G3-G4 in FIG. 46E is illustrated in FIG. 47A. The direction of dashed-dotted line G1-G2 is referred to as a channel length direction, and the direction of dashed-dotted line G3-G4 is referred to as a channel width direction in some cases.

The transistor 406 is different from the transistor 403 in that the conductive layer 440 includes two layers, the conductive layers 441 and 442, and the conductive layer 450 includes two layers, the conductive layers 451 and 452.

In the structures of the transistors 405 and 406, the conductive layers 440 and 450 are not in contact with the insulating layer 420. These structures make the insulating layer 420 less likely to be deprived of oxygen by the conductive layers 440 and 450 and facilitate oxygen supply from the insulating layer 420 to the oxide semiconductor layer 430.

An impurity for forming an oxygen vacancy to increase conductivity may be added to the regions 534 and 535 in the transistor 403, the transistor 404, and the transistor 406. As an impurity for forming an oxygen vacancy in an oxide semiconductor layer, for example, one or more of the following can be used: phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon. As a method for adding the impurity, plasma treatment, ion implantation, ion doping, plasma immersion ion implantation, or the like can be used.

When the above element is added as an impurity element to the oxide semiconductor layer, a bond between a metal element and oxygen in the oxide semiconductor layer is cut, so that an oxygen vacancy is formed. Interaction between an oxygen vacancy in the oxide semiconductor layer and hydrogen that remains in the oxide semiconductor layer or is added to the oxide semiconductor layer later can increase the conductivity of the oxide semiconductor layer.

When hydrogen is added to an oxide semiconductor in which an oxygen vacancy is formed by addition of an impurity element, hydrogen enters an oxygen vacant site and forms a donor level in the vicinity of the conduction band. Consequently, an oxide conductor can be formed. Here, an oxide conductor refers to an oxide semiconductor having become a conductor. Note that the oxide conductor has a light-transmitting property like the oxide semiconductor.

The oxide conductor is a degenerated semiconductor and it is suggested that the conduction band edge equals or substantially equals the Fermi level. For that reason, an ohmic contact is made between an oxide conductor layer and conductive layers that function as a source and a drain; thus, contact resistance between the oxide conductor layer and the conductive layers that function as a source and a drain can be reduced.

Although the transistors 401 to 406 in FIGS. 45A to 45F, FIGS. 46A to 46F, and FIGS. 47A to 47D are examples in which the oxide semiconductor layer 430 is a single layer, the oxide semiconductor layer 430 may be a stacked layer. FIG. 48A is a top view of the oxide semiconductor layer 430, and FIGS. 48B and 48C are cross-sectional views of the oxide semiconductor layer 430 having a two-layer structure of an oxide semiconductor layer 430 a and an oxide semiconductor layer 430 b. FIGS. 48D and 48E are cross-sectional views of the oxide semiconductor layer 430 having a three-layer structure of the oxide semiconductor layer 430 a, the oxide semiconductor layer 430 b, and an oxide semiconductor layer 430 c.

The oxide semiconductor layers 430 a and 430 c can also be referred to as insulating layers because no channel region is formed therein.

Oxide semiconductor layers with different compositions, for example, can be used as the oxide semiconductor layers 430 a, 430 b, and 430 c.

The oxide semiconductor layer 430 in the transistors 401 to 406 can be replaced by the oxide semiconductor layer 430 in FIGS. 48B and 48C or FIGS. 48D and 48E.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 49A to 49F, FIGS. 50A to 50F, and FIGS. 51A to 51D. FIGS. 49A, 49C, and 49E and FIGS. 50A, 50C, and 50E are top views of transistors 407, 408, 409, 410, 411, and 412, respectively. FIG. 49B is a cross section in the direction of dashed-dotted line H1-H2 in FIG. 49A. FIG. 49D is a cross section in the direction of dashed-dotted line I1-I2 in FIG. 49C. FIG. 49F is a cross section in the direction of dashed-dotted line J1-J2 in FIG. 49E. FIG. 50B is a cross section in the direction of dashed-dotted line K1-K2 in FIG. 50A. FIG. 50D is a cross section in the direction of dashed-dotted line L1-L2 in FIG. 50C. FIG. 50F is a cross section in the direction of dashed-dotted line M1-M2 in FIG. 50E. FIG. 51A illustrates each of cross sections in the directions of dashed-dotted lines H3-H4 in FIG. 49A, J3-J4 in FIG. 49E, K3-K4 in FIG. 50A, L3-L4 in FIG. 50C, and M3-M4 in FIG. 50E. FIG. 51B is a cross section in the direction of dashed-dotted line I3-I4 in FIG. 49C. The directions of dashed-dotted lines H1-H2, I1-I2, J1-J2, K1-K2, L1-L2, and M1-M2 may be each referred to as a channel length direction, and the directions of dashed-dotted lines H3-H4, I3-I4, J3-J4, K3-K4, L3-L4, and M3-M4 may be each referred to as a channel width direction.

The transistors 407 and 408 each have the same structure as the transistors 401 and 402 except that the oxide semiconductor layer 430 includes two layers (the oxide semiconductor layers 430 a and 430 b) in the regions 531 and 532, that the oxide semiconductor layer 430 includes three layers (the oxide semiconductor layers 430 a to 430 c) in the region 533, and that part of the oxide semiconductor layer (the oxide semiconductor layer 430 c) exists between the insulating layer 460 and the conductive layers 440 and 450.

The transistors 409, 410, and 412 each have the same structure as the transistors 403, 404, and 406 except that the oxide semiconductor layer 430 includes two layers (the oxide semiconductor layers 430 a and 430 b) in the regions 531, 532, 534, and 535 and that the oxide semiconductor layer 430 includes three layers (the oxide semiconductor layers 430 a to 430 c) in the region 533.

The transistor 411 has the same structure as the transistor 405 except that the oxide semiconductor layer 430 includes two layers (the oxide semiconductor layers 430 a and 430 b) in the regions 531 and 532, that the oxide semiconductor layer 430 includes three layers (the oxide semiconductor layers 430 a to 430 c) in the region 533, and that part of the oxide semiconductor layer (the oxide semiconductor layer 430 c) exists between the insulating layer 460 and the conductive layers 441 and 451.

The transistor in one embodiment of the present invention may include a conductive layer 473 between the oxide semiconductor layer 430 and the substrate 415 as illustrated in cross-sectional views in the channel length directions of the transistors 401 to 412 illustrated in FIGS. 52A to 52F and FIGS. 53A to 53F, the cross-sectional view in the channel width direction of each of the transistors 401 to 406 illustrated in FIG. 47C, and the cross-sectional view in the channel width direction of each of the transistors 407 to 412 illustrated in FIG. 51C. The conductive layer 473 is used as a second gate electrode (also referred to as a back gate electrode), whereby the channel formation region in the oxide semiconductor layer 430 is electrically surrounded by the conductive layers 470 and 473. Such a transistor structure is referred to as a surrounded channel (s-channel) structure. Such a structure can increase the on-state current, and can control the threshold voltage. In the cross-sectional views in FIGS. 52A to 52F and FIGS. 53A to 53F, the width of the conductive layer 473 may be smaller than that of the oxide semiconductor layer 430. Moreover, the width of the conductive layer 473 may be shorter than that of the conductive layer 470.

In order to increase the on-state current, for example, the conductive layers 470 and 473 are made to have the same potential, and the transistor is driven as a double-gate transistor. Furthermore, in order to control the threshold voltage, a fixed potential that is different from the potential of the conductive layer 470 is applied to the conductive layer 473. To set the conductive layers 470 and 473 at the same potential, for example, as illustrated in FIG. 47D and FIG. 51D, the conductive layers 470 and 473 may be electrically connected to each other through a contact hole.

The transistor in one embodiment of the present invention may have a structure illustrated in FIGS. 54A to 54C. FIG. 54A is a top view. FIG. 54B illustrates a cross-sectional view taken along dashed-dotted line N1-N2 in FIG. 54A. FIG. 54C illustrates a cross-sectional view taken along dashed-dotted line N3-N4 in FIG. 54A. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG. 54A.

In a transistor 413, the insulating layer 420 is in contact with the substrate 415; the oxide semiconductor layer 430 (the oxide semiconductor layers 430 a to 430 c) is in contact with the insulating layer 420; the conductive layer 440 and the conductive layer 450 are in contact with the oxide semiconductor layer 430 b; the insulating layer 460 is in contact with the oxide semiconductor layer 430 c; the conductive layer 470 is in contact with the insulating layer 460; and the insulating layer 480 is in contact with the insulating layer 420, the conductive layer 440, and the conductive layer 450. Note that the oxide semiconductor layer 430 c, the insulating layer 460, and the conductive layer 470 are provided in an opening reaching the oxide semiconductor layer 430 b in the insulating layer 480.

In the transistor 413, a region where the conductive layer 470 overlaps with the conductive layer 440 or the conductive layer 450 is smaller than that in any other transistors described above; thus, the parasitic capacitance in the transistor 413 can be reduced. Accordingly, the transistor 413 is suitable for a component of a circuit that requires high-speed operation. As illustrated in FIGS. 54B and 54C, the transistor 413 is preferably subjected to a chemical mechanical polishing (CMP) method or the like to have a flat top surface, although not necessarily.

The conductive layer 440 and the conductive layer 450 in the transistor in one embodiment of the present invention may each have a width (WsD) longer than the width (Wos) of the oxide semiconductor layer as illustrated in the top view in FIG. 55A or shorter as illustrated in the top view in FIG. 55B. When Wos WSD (WSD is less than or equal to Wos) is satisfied, a gate electric field is easily applied to the entire oxide semiconductor layer 430, so that electrical characteristics of the transistor can be particularly improved. As illustrated in FIG. 55C, the conductive layers 440 and 450 may be formed only in regions overlapping with the oxide semiconductor layer 430.

Note that FIGS. 55A to 55C only illustrate the oxide semiconductor layer 430, the conductive layer 440, and the conductive layer 450.

In the transistor including the oxide semiconductor layers 430 a and 430 b and the transistor including the oxide semiconductor layers 430 a to 430 c, selecting appropriate materials for the two or three layers forming the oxide semiconductor layer 430 makes current flow to the oxide semiconductor layer 430 b. Since current flows to the oxide semiconductor layer 430 b, the current is hardly influenced by interface scattering, leading to a high on-state current. Thus, increasing the thickness of the oxide semiconductor layer 430 b improves the on-state current in some cases.

A semiconductor device including a transistor with any of the above structures can have favorable electrical characteristics.

The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

Embodiment 6

In this embodiment, components of the transistors described in Embodiment 5 are described in detail.

Note that there is no particular limitation on the type of the substrate 415. As the substrate 415, a semiconductor substrate (e.g., a single crystal substrate or a silicon substrate), an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a stainless steel substrate, a substrate including stainless steel foil, a tungsten substrate, a substrate including tungsten foil, a flexible substrate, an attachment film, paper including a fibrous material, a base material film, or the like can be used, for example. As an example of a glass substrate, a barium borosilicate glass substrate, an aluminoborosilicate glass substrate, soda lime glass substrate, and the like can be given. Examples of the flexible substrate, the attachment film, the base material film, and the like are substrates of plastics typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Alternatively, a film of polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, or the like can be used. Alternatively, polyamide, polyimide, aramid, epoxy, an inorganic vapor deposition film, paper, or the like can be used. Specifically, the use of semiconductor substrates, single crystal substrates, SOI substrates, or the like enables the manufacture of small-sized transistors with a small variation in characteristics, size, shape, or the like and with high current capability. A circuit using such transistors achieves lower power consumption of the circuit or higher integration of the circuit.

As the substrate 415, a silicon substrate provided with a transistor, or the silicon substrate over which an insulating layer, a wiring, a conductor that functions as a contact plug, and the like are provided can be used. Note that when only p-ch transistors are formed using the silicon substrate, a silicon substrate with n⁻-type conductivity is preferably used. Alternatively, an SOI substrate including an n⁻-type or i-type silicon layer may be used. A surface of the silicon substrate where the transistor is formed preferably has a (110) plane orientation. Forming a p-ch transistor with the (110) plane can increase mobility.

A flexible substrate may be used as the substrate 415, and the transistor may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. The separation layer can be used when part or the whole of a semiconductor device formed over the separation layer is separated from the substrate and transferred to another substrate. In such a case, the transistor can be transferred to a substrate having low heat resistance or a flexible substrate as well. For the separation layer, a stack including inorganic films, which are a tungsten film and a silicon oxide film, or a resin film of polyimide or the like formed over a substrate can be used, for example.

In other words, a transistor may be formed using one substrate and then transferred to another substrate. Examples of a substrate to which a transistor is transferred include, in addition to the above-described substrates over which transistors can be formed, a paper substrate, a cellophane substrate, an aramid film substrate, a polyimide film substrate, a stone substrate, a wood substrate, a cloth substrate (including a natural fiber (e.g., silk, cotton, or hemp), a synthetic fiber (e.g., nylon, polyurethane, or polyester), a regenerated fiber (e.g., acetate, cupra, rayon, or regenerated polyester), or the like), a leather substrate, a rubber substrate, and the like. By using such a substrate, a transistor with excellent properties or a transistor with low power consumption can be formed, a device with high durability can be formed, heat resistance can be provided, or reduction in weight or thickness can be achieved.

The insulating layer 420 can have a function of supplying oxygen to the oxide semiconductor layer 430 as well as a function of preventing diffusion of impurities from a component included in the substrate 415. For this reason, the insulating layer 420 is preferably an insulating layer containing oxygen and further preferably, the insulating layer 420 is an insulating layer containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. The insulating layer 420 is, for example, a film in which the amount of released oxygen when converted into oxygen atoms is greater than or equal to 1.0×10¹⁹ atoms/cm³ in thermal desorption spectroscopy (TDS) analysis. In the TDS analysis, the film surface temperature is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C. In the case where the substrate 415 is provided with another device, the insulating layer 420 also functions as an interlayer insulating layer. In that case, the insulating layer 420 is preferably subjected to planarization treatment such as CMP treatment so as to have a flat surface.

For example, the insulating layer 420 can be formed using an oxide insulating layer including aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating layer including silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a mixed material of any of these. The insulating layer 420 may be a stack of any of the above materials.

In this embodiment, detailed description is given mainly on the case where the oxide semiconductor layer 430 of the transistor has a three-layer structure in which the oxide semiconductor layers 430 a, 430 b, and 430 c are sequentially stacked from the insulating layer 420 side.

Note that in the case where the oxide semiconductor layer 430 is a single layer, a layer corresponding to the oxide semiconductor layer 430 b described in this embodiment is used.

In the case where the oxide semiconductor layer 430 has a two-layer structure, a stack in which layers corresponding to the oxide semiconductor layer 430 a and the oxide semiconductor layer 430 b described in this embodiment are sequentially stacked from the insulating layer 420 side is used. In such a case, the oxide semiconductor layers 430 a and 430 b can be replaced with each other.

In the case where the oxide semiconductor layer 430 has a layered structure of four or more layers, for example, a structure in which another oxide semiconductor layer is added to the three-layer stack of the oxide semiconductor layer 430 described in this embodiment can be employed.

For the oxide semiconductor layer 430 b, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the oxide semiconductor layers 430 a and 430 c is used. The electron affinity can be obtained by subtracting an energy difference between the conduction band minimum and the valence band maximum (what is called an energy gap) from an energy difference between the vacuum level and the valence band maximum (what is called an ionization potential).

The oxide semiconductor layers 430 a and 430 c each contain one or more kinds of metal elements contained in the oxide semiconductor layer 430 b. For example, the oxide semiconductor layers 430 a and 430 c are preferably formed using an oxide semiconductor whose conduction band minimum is closer to a vacuum level than that of the oxide semiconductor layer 430 b by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

In such a structure, when an electric field is applied to the conductive layer 470, a channel is formed in the oxide semiconductor layer 430 b whose conduction band minimum is the lowest in the oxide semiconductor layer 430.

Furthermore, since the oxide semiconductor layer 430 a contains one or more kinds of metal elements contained in the oxide semiconductor layer 430 b, an interface state is unlikely to be formed at the interface between the oxide semiconductor layers 430 a and 430 b, compared with the interface between the oxide semiconductor layer 430 b and the insulating layer 420 on the assumption that the oxide semiconductor layer 430 b is in contact with the insulating layer 420. The interface state sometimes forms a channel; therefore, the threshold voltage of the transistor is changed in some cases. Thus, with the oxide semiconductor layer 430 a, variations in electrical characteristics of the transistor, such as a threshold voltage, can be reduced. Moreover, the reliability of the transistor can be improved.

Since the oxide semiconductor layer 430 c contains one or more kinds of metal elements contained in the oxide semiconductor layer 430 b, scattering of carriers is unlikely to occur at the interface between the oxide semiconductor layers 430 b and 430 c, compared with the interface between the oxide semiconductor layer 430 b and the gate insulating layer (the insulating layer 460) on the assumption that the oxide semiconductor layer 430 b is in contact with the gate insulating layer. Thus, with the oxide semiconductor layer 430 c, the field-effect mobility of the transistor can be increased.

For the oxide semiconductor layers 430 a and 430 c, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf with a higher atomic ratio than that used for the oxide semiconductor layer 430 b can be used. Specifically, the atomic ratio of any of the above metal elements in the oxide semiconductor layers 430 a and 430 c is 1.5 times or more, preferably 2 times or more, and further preferably 3 times or more as large as that in the oxide semiconductor layer 430 b. Any of the above metal elements is strongly bonded to oxygen and thus can have a function of suppressing generation of an oxygen vacancy in the oxide semiconductor layers 430 a and 430 c. That is, an oxygen vacancy is less likely to be generated in the oxide semiconductor layers 430 a and 430 c than in the oxide semiconductor layer 430 b.

An oxide semiconductor that can be used for each of the oxide semiconductor layers 430 a, 430 b, and 430 c preferably contains at least In or Zn. Both In and Zn are preferably contained. In order to reduce variations in electrical characteristics of the OS transistor, a stabilizer is preferably contained in addition to In and Zn.

Examples of a stabilizer include Ga, Sn, Hf, Al, and Zr. Other examples of the stabilizer include lanthanoids such as La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu.

As the oxide semiconductor, for example, any of the following can be used: indium oxide, tin oxide, gallium oxide, zinc oxide, an In—Zn oxide, a Sn—Zn oxide, an Al—Zn oxide, a Zn—Mg oxide, a Sn—Mg oxide, an In—Mg oxide, an In—Ga oxide, an In—Ga—Zn oxide, an In—Al—Zn oxide, an In—Sn—Zn oxide, a Sn—Ga—Zn oxide, an Al—Ga—Zn oxide, a Sn—Al—Zn oxide, an In—Hf—Zn oxide, an In—La—Zn oxide, an In—Ce—Zn oxide, an In—Pr—Zn oxide, an In—Nd—Zn oxide, an In—Sm—Zn oxide, an In—Eu—Zn oxide, an In—Gd—Zn oxide, an In—Tb—Zn oxide, an In—Dy—Zn oxide, an In—Ho—Zn oxide, an In—Er—Zn oxide, an In—Tm—Zn oxide, an In—Yb—Zn oxide, an In—Lu—Zn oxide, an In—Sn-Ga—Zn oxide, an In—Hf-Ga—Zn oxide, an In—Al-Ga—Zn oxide, an In—Sn—Al—Zn oxide, an In—Sn—Hf—Zn oxide, and an In—Hf—Al—Zn oxide.

For example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain another metal element in addition to In, Ga, and Zn. In this specification, a film containing the In—Ga—Zn oxide is also referred to as an IGZO film.

A material represented by InMO₃(ZnO)_(m) (m>0, where m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, and Nd. Alternatively, a material represented by In₂SnO₅(ZnO)_(n) (n>0, where n is an integer) may be used.

Note that when each of the oxide semiconductor layers 430 a, 430 b, and 430 c is an In-M-Zn oxide containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), in the case where the oxide semiconductor layer 430 a has an atomic ratio of In to M and Zn that is x₁:y₁:z₁, the oxide semiconductor layer 430 b has an atomic ratio of In to M and Zn that is x₂:y₂:z₂, and the oxide semiconductor layer 430 c has an atomic ratio of In to M and Zn that is x₃:y₃:z₃, each of y₁/x₁ and y₃/x₃ is preferably larger than y₂/x₂. Each of y₁/x₁ and y₃/x₃ is 1.5 times or more, preferably 2 times or more, and further preferably 3 times or more as large as y₂/x₂. At this time, when y₂ is greater than or equal to x₂ in the oxide semiconductor layer 430 b, the transistor can have stable electrical characteristics. However, when y₂ is 3 times or more as large as x₂, the field-effect mobility of the transistor is reduced; accordingly, y₂ is preferably smaller than 3 times x₂.

In the case where Zn and O are not taken into consideration, the proportion of In and the proportion of Min each of the oxide semiconductor layers 430 a and 430 c are preferably less than 50 atomic % and greater than 50 atomic %, respectively, and further preferably less than 25 atomic % and greater than 75 atomic %, respectively. Furthermore, in the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in the oxide semiconductor layer 430 b are preferably greater than 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than 34 atomic % and less than 66 atomic %, respectively.

The indium content in the oxide semiconductor layer 430 b is preferably higher than those in the oxide semiconductor layers 430 a and 430 c. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide in which the proportion of In is higher than that of M has higher mobility than an oxide in which the proportion of In is equal to or lower than that of M. Thus, with the use of an oxide having a high content of indium for the oxide semiconductor layer 430 b, a transistor having high field-effect mobility can be obtained.

The thickness of the oxide semiconductor layer 430 a is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, and further preferably greater than or equal to 5 nm and less than or equal to 25 nm. The thickness of the oxide semiconductor layer 430 b is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 5 nm and less than or equal to 150 nm, and further preferably greater than or equal to 10 nm and less than or equal to 100 nm. The thickness of the oxide semiconductor layer 430 c is greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 2 nm and less than or equal to 30 nm, and further preferably greater than or equal to 3 nm and less than or equal to 15 nm. In addition, the oxide semiconductor layer 430 b is preferably thicker than the oxide semiconductor layer 430 c.

In order that a transistor in which a channel is formed in an oxide semiconductor layer have stable electrical characteristics, it is effective to make the oxide semiconductor layer intrinsic or substantially intrinsic by reducing the concentration of impurities in the oxide semiconductor layer. The term “substantially intrinsic” refers to a state where an oxide semiconductor layer has a carrier density lower than 1×10¹⁵/cm³, lower than 1×10¹³/cm³, lower than 8×10¹¹/cm³, or lower than 1×10⁸/cm³, and is higher than or equal to 1×10⁻⁹/cm³.

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than main components of the oxide semiconductor layer are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density, and silicon forms impurity levels in the oxide semiconductor layer. The impurity levels serve as traps and might cause deterioration of electrical characteristics of the transistor. Therefore, it is preferable to reduce the concentration of the impurities in the oxide semiconductor layers 430 a, 430 b, and 430 c and at interfaces between the oxide semiconductor layers.

In order to form an intrinsic or substantially intrinsic oxide semiconductor layer, the oxide semiconductor layer is arranged to have a region in which the concentration of silicon estimated by secondary ion mass spectrometry (SIMS) is lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, and further preferably lower than 1×10¹⁸ atoms/cm³. The oxide semiconductor layer is arranged to have a region in which the concentration of hydrogen is lower than or equal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹ atoms/cm³, further preferably lower than or equal to 1×10¹⁹ atoms/cm³, and still further preferably lower than or equal to 5×10¹⁸ atoms/cm³. The concentration of nitrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 5×10¹⁹ atoms/cm³, preferably lower than or equal to 5×10¹⁸ atoms/cm³, further preferably lower than or equal to 1×10¹⁸ atoms/cm³, and still further preferably lower than or equal to 5×10¹⁷ atoms/cm³.

The high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor layer. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the oxide semiconductor layer is controlled to have a region in which the concentration of silicon is lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, and further preferably lower than 1×10¹⁸ atoms/cm³. Furthermore, the oxide semiconductor layer is controlled to have a region in which the concentration of carbon is lower than 1×10¹⁹ atoms/cm³, preferably lower than 5×10¹⁸ atoms/cm³, and further preferably lower than 1×10¹⁸ atoms/cm³.

As described above, a transistor in which a highly purified oxide semiconductor layer is used for a channel formation region exhibits an extremely low off-state current. When voltage between a source and a drain is set at about 0.1 V, 5 V, or 10 V, for example, the off-state current per channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.

As the gate insulating layer of the transistor, an insulating layer containing silicon is used in many cases; thus, it is preferable that, as in the transistor in one embodiment of the present invention, a region of the oxide semiconductor layer that serves as a channel not be in contact with the gate insulating layer for the above reason. In the case where a channel is formed at the interface between the gate insulating layer and the oxide semiconductor layer, scattering of carriers occurs at the interface, so that the field-effect mobility of the transistor is reduced in some cases. Also from the view of the above, it is preferable that the region of the oxide semiconductor layer that serves as a channel be separated from the gate insulating layer.

Accordingly, with the oxide semiconductor layer 430 having a layered structure including the oxide semiconductor layers 430 a, 430 b, and 430 c, a channel can be formed in the oxide semiconductor layer 430 b; thus, the transistor can have high field-effect mobility and stable electrical characteristics.

In a band structure, the conduction band minimums of the oxide semiconductor layers 430 a, 430 b, and 430 c are continuous. This can be understood also from the fact that the compositions of the oxide semiconductor layers 430 a, 430 b, and 430 c are close to one another and oxygen is easily diffused among the oxide semiconductor layers 430 a, 430 b, and 430 c. Thus, the oxide semiconductor layers 430 a, 430 b, and 430 c have a continuous physical property though they have different compositions and form a stack. In the drawings, interfaces between the oxide semiconductor layers of the stack are indicated by dotted lines.

The oxide semiconductor layer 430 in which layers containing the same main components are stacked is formed to have not only a simple layered structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which the conduction band minimums are continuous (U-shape well)). In other words, the layered structure is formed such that there exists no impurity that forms a defect level such as a trap center or a recombination center at each interface. If impurities exist between the stacked oxide semiconductor layers, the continuity of the energy band is lost and carriers disappear because of a trap or recombination at the interface.

For example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 can be used for the oxide semiconductor layers 430 a and 430 c, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 2:1:3, 5:5:6, or 3:1:2 can be used for the oxide semiconductor layer 430 b. In each of the oxide semiconductor layers 430 a to 430 c, the proportion of each atom in the atomic ratio varies within a range of ±40% as a margin.

The atomic ratio of In to Ga and Zn is not necessarily an integer ratio.

The oxide semiconductor layer 430 b of the oxide semiconductor layer 430 serves as a well, so that a channel is formed in the oxide semiconductor layer 430 b. Since the conduction band minimums are continuous, the oxide semiconductor layer 430 can also be referred to as a U-shaped well. Furthermore, a channel formed to have such a structure can also be referred to as a buried channel.

Trap levels due to impurities or defects might be formed in the vicinity of the interface between an insulating layer such as a silicon oxide film and each of the oxide semiconductor layers 430 a and 430 c. The oxide semiconductor layer 430 b can be distanced away from the trap levels owing to the existence of the oxide semiconductor layers 430 a and 430 c.

However, when the energy differences between the conduction band minimum of the oxide semiconductor layer 430 b and the conduction band minimum of each of the oxide semiconductor layers 430 a and 430 c are small, an electron in the oxide semiconductor layer 430 b might reach the trap level by passing over the energy differences. When the electron is trapped in the trap level, negative charge is generated at the interface with the insulating layer, so that the threshold voltage of the transistor is shifted in the positive direction.

The oxide semiconductor layers 430 a, 430 b, and 430 c preferably include crystal parts. In particular, when crystals with c-axis alignment are used, the transistor can have stable electrical characteristics. Moreover, crystals with c-axis alignment are resistant to bending; therefore, using such crystals can improve the reliability of a semiconductor device using a flexible substrate.

As the conductive layer 440 functioning as one of a source and a drain and the conductive layer 450 functioning as the other of the source and the drain, for example, a single layer or a stacked layer formed using a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, and Sc and alloys of any of these metal materials can be used. It is preferable to use Ti, which is particularly easily bonded to oxygen, or W, which has a high melting point and thus allows subsequent processes to be performed at relatively high temperatures, as a typical example. It is also possible to use a stack of any of the above materials and Cu or an alloy such as Cu—Mn, which has low resistance. In the transistors 405, 406, 411, and 412, for example, it is possible to use W for the conductive layers 441 and 451 and use a stack of Ti and Al for the conductive layers 442 and 452.

The above materials are capable of extracting oxygen from an oxide semiconductor layer. Therefore, in a region of the oxide semiconductor layer that is in contact with any of the above materials, oxygen is released from the oxide semiconductor layer and an oxygen vacancy is formed. Hydrogen slightly contained in the layer and the oxygen vacancy are bonded to each other, so that the region is markedly changed to an n-type region. Accordingly, the n-type region can serve as a source or a drain of the transistor.

In the case where W is used for the conductive layers 440 and 450, the conductive layers 440 and 450 may be doped with nitrogen. Doping with nitrogen can appropriately lower the capability of extracting oxygen and prevent the n-type region from spreading to a channel region. It is possible to prevent the n-type region from spreading to a channel region also by using a stack of W and an n-type semiconductor layer as the conductive layers 440 and 450 and putting the n-type semiconductor layer in contact with the oxide semiconductor layer. As the n-type semiconductor layer, an In—Ga—Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like to which nitrogen is added can be used.

The insulating layer 460 functioning as a gate insulating layer can be formed using an insulating layer containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer 460 may be a stack including any of the above materials. The insulating layer 460 may contain La, N, Zr, or the like as an impurity.

An example of a layered structure of the insulating layer 460 is described. The insulating layer 460 includes, for example, oxygen, nitrogen, silicon, or hafnium. Specifically, the insulating layer 460 preferably includes hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide and aluminum oxide have higher dielectric constants than silicon oxide and silicon oxynitride. Therefore, the insulating layer 460 using hafnium oxide or aluminum oxide can have larger thickness than the insulating layer 460 using silicon oxide, so that leakage current due to tunnel current can be reduced. That is, a transistor with a low off-state current can be provided. Moreover, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to provide a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to these examples.

For the insulating layers 420 and 460 in contact with the oxide semiconductor layer 430, a film that releases less nitrogen oxide is preferably used. In the case where the oxide semiconductor is in contact with an insulating layer that releases a large amount of nitrogen oxide, the density of states due to nitrogen oxide increases in some cases. The density of states due to nitrogen oxide can be formed in the energy gap of the oxide semiconductor. For the insulating layers 420 and 460, for example, an oxide insulating layer such as a silicon oxynitride film or an aluminum oxynitride film that releases less nitrogen oxide can be used.

A silicon oxynitride film that releases less nitrogen oxide is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide in TDS; the amount of released ammonia is typified by greater than or equal to 1×10¹⁸ molecules/cm³ and less than or equal to 5×10¹⁹ molecules/cm³. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of the film becomes higher than or equal to 50° C. and lower than or equal to 650° C., and preferably higher than or equal to 50° C. and lower than or equal to 550° C.

By using the above oxide insulating layer for the insulating layers 420 and 460, a shift in the threshold voltage of the transistor can be reduced, which leads to reduced fluctuations in the electrical characteristics of the transistor.

For the conductive layer 470 functioning as a gate, for example, a conductive layer formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, or W can be used. Alternatively, an alloy or a conductive nitride of any of these materials may be used. Alternatively, a stack of a plurality of materials selected from these materials, alloys of these materials, and conductive nitrides of these materials may be used. As a typical example, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. Alternatively, Cu or an alloy such as Cu—Mn, which has low resistance, or a stack of any of the above materials and Cu or an alloy such as Cu—Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer 471 and tungsten is used for the conductive layer 472 to form the conductive layer 470.

As the insulating layer 475, a silicon nitride film, an aluminum nitride film, or the like containing hydrogen can be used. In the transistors 403, 404, 406, 409, 410, and 412, the use of an insulating layer containing hydrogen is used as the insulating layer 475 allows the oxide semiconductor layer 430 to be partly changed to n-type because the oxide semiconductor layer 430 is partly in contact with the insulating layer 475. In addition, a nitride insulating layer functions as a blocking film against moisture and the like and can improve the reliability of the transistor.

An aluminum oxide film can also be used as the insulating layer 475. It is particularly preferable to use an aluminum oxide film as the insulating layer 475 in the transistors 401, 402, 405, 407, 408, and 411. The aluminum oxide film has a significant effect of blocking both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can suitably function as a protective film that has effects of preventing entry of impurities such as hydrogen and moisture into the oxide semiconductor layer 430, preventing release of oxygen from the oxide semiconductor layer, and preventing unnecessary release of oxygen from the insulating layer 420. Furthermore, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

Furthermore, the insulating layer 480 is preferably formed over the insulating layer 475. The insulating layer 480 can be formed using an insulating layer containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer 480 may be a stack of any of the above materials.

Here, like the insulating layer 420, the insulating layer 480 preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer 480 can be diffused into the channel formation region in the oxide semiconductor layer 430 through the insulating layer 460, so that oxygen vacancies formed in the channel formation region can be filled with oxygen. In this manner, stable electrical characteristics of the transistor can be achieved.

High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics of the transistor. In particular, a decrease in channel width causes a reduction in on-state current.

In the transistors 407 to 412 in one embodiment of the present invention, the oxide semiconductor layer 430 c is formed to cover the oxide semiconductor layer 430 b where a channel is formed; thus, a channel formation layer is not in contact with the gate insulating layer. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating layer can be reduced and the on-state current of the transistor can be increased.

In the transistor in one embodiment of the present invention, as described above, the gate (the conductive layer 470) is formed to electrically surround the oxide semiconductor layer 430 in the channel width direction; accordingly, a gate electric field is applied to the oxide semiconductor layer 430 in the direction perpendicular to the side surface in addition to the direction perpendicular to the top surface. In other words, a gate electric field is applied to the entire channel formation layer and an effective channel width is increased, leading to a further increase in on-state current.

Furthermore, in the transistor in one embodiment of the present invention in which the oxide semiconductor layer 430 has a two-layer structure or a three-layer structure, since the oxide semiconductor layer 430 b where a channel is formed is provided over the oxide semiconductor layer 430 a, an interface state is less likely to be formed. In the transistor in one embodiment of the present invention in which the oxide semiconductor layer 430 has a three-layer structure, since the oxide semiconductor layer 430 b is positioned at the middle of the three-layer structure, the influence of an impurity that enters from upper and lower layers on the oxide semiconductor layer 430 b can also be eliminated. Therefore, the transistor can achieve not only the increase in on-state current but also stabilization of the threshold voltage and a reduction in S value (subthreshold value). Thus, current at a gate voltage VG of 0 V can be reduced and power consumption can be reduced. In addition, since the threshold voltage of the transistor becomes stable, long-term reliability of the semiconductor device can be improved. Furthermore, the transistor in one embodiment of the present invention is suitable for a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization is reduced.

Although the variety of films such as the metal films, the semiconductor films, and the inorganic insulating films that are described in this embodiment typically can be formed by sputtering or plasma-enhanced chemical vapor deposition (CVD), such films may be formed by another method such as thermal CVD. Examples of the thermal CVD include MOCVD and atomic layer deposition (ALD).

Since plasma is not used for deposition, thermal CVD has an advantage that no defect due to plasma damage is generated.

Deposition by thermal CVD may be performed in such a manner that a source gas and an oxidizer are supplied to the chamber at the same time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate.

Deposition by ALD is performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are introduced into the chamber and reacted, and then the sequence of gas introduction is repeated. An inert gas (e.g., argon or nitrogen) may be introduced as a carrier gas with the source gases. For example, two or more kinds of source gases may be sequentially supplied to the chamber. In that case, after reaction of a first source gas, an inert gas is introduced, and then a second source gas is introduced so that the source gases are not mixed. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate and reacted to form a first layer, and then, the second source gas introduced is adsorbed and reacted. That is, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of gas introduction is controlled and repeated more than once until desired thickness is obtained, so that a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of gas introduction; therefore, ALD makes it possible to accurately adjust thickness and thus is suitable for manufacturing a minute FET.

The variety of films such as the metal film, the semiconductor film, and the inorganic insulating film that have been disclosed in the above embodiments can be formed by thermal CVD such as MOCVD or ALD. For example, in the case where an In—Ga—Zn—O film is formed, trimethylindium (In(CH₃)₃), trimethylgallium (Ga(CH₃)₃), and dimethylzinc (Zn(CH₃)₂) can be used. Without limitation to the above combination, triethylgallium (Ga(C₂H₅)₃) can be used instead of trimethylgallium and diethylzinc (Zn(C₂H₅)₂) can be used instead of dimethylzinc.

For example, in the case where a hafnium oxide film is formed with a deposition apparatus using ALD, two kinds of gases, i.e., ozone (O₃) as an oxidizer and a source material gas that is obtained by vaporizing liquid containing a solvent and a hafnium precursor (hafnium alkoxide and a hafnium amide such as tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH₃)₂]₄) and tetrakis(ethylmethylamide)hafnium) are used.

For example, in the case where an aluminum oxide film is formed with a deposition apparatus using ALD, two kinds of gases, i.e., H₂O as an oxidizer and a source gas that is obtained by vaporizing liquid containing a solvent and an aluminum precursor (e.g., trimethylaluminum (TMA, Al(CH₃)₃)) are used. Examples of another material include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed with a deposition apparatus using ALD, hexachlorodisilane is adsorbed on a surface where a film is to be formed, and radicals of an oxidizing gas (e.g., O₂ or dinitrogen monoxide) are supplied to react with an adsorbate.

For example, in the case where a tungsten film is formed with a deposition apparatus using ALD, a WF₆ gas and a B₂H₆ gas are sequentially introduced to form an initial tungsten film, and then a WF₆ gas and an H₂ gas are sequentially introduced to form a tungsten film. Note that an SiH₄ gas may be used instead of a B₂H₆ gas.

For example, in the case where an oxide semiconductor layer, e.g., an In—Ga—Zn—O film is formed with a deposition apparatus using ALD, an In(CH₃)₃ gas and an O₃ gas) are sequentially introduced to form an In—O layer, a Ga(CH₃)₃ gas and an O₃ gas) are sequentially introduced to form a Ga—O layer, and then a Zn(CH₃)₂ gas and an O₃ gas) are sequentially introduced to form a Zn—O layer. Note that the order of these layers is not limited to this example. An In—Ga—O layer, an In—Zn—O layer, a Ga—Zn—O layer, or the like may be formed using these gases. Although an H₂O gas that is obtained by bubbling with an inert gas such as Ar may be used instead of an O₃ gas), it is preferable to use an O₃ gas), which does not contain H.

A facing-target-type sputtering apparatus can be used for deposition of an oxide semiconductor layer. Deposition using the facing-target-type sputtering apparatus can also be referred to as vapor deposition SP (VDSP).

When an oxide semiconductor layer is deposited using a facing-target-type sputtering apparatus, plasma damage to the oxide semiconductor layer at the time of deposition can be reduced. Thus, oxygen vacancies in the film can be reduced. In addition, the use of the facing-target-type sputtering apparatus enables low-pressure deposition. Accordingly, the concentration of impurities (e.g., hydrogen, a rare gas (e.g., argon), and water) in a deposited oxide semiconductor layer can be lowered.

The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

Embodiment 7

A structure of an oxide semiconductor layer that can be used in one embodiment of the present invention is described below.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. The term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

An amorphous structure is generally thought to be isotropic and have no non-uniform structure, to be metastable and have no fixed positions of atoms, to have a flexible bond angle, and to have a short-range order but have no long-range order, for example.

In other words, a stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. In contrast, an a-like OS, which is not isotropic, has an unstable structure that contains a void. Because of its instability, an a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

Analysis of a CAAC-OS by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal that is classified into the space group R-3m is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 56A. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or the top surface of the CAAC-OS film. Note that a peak sometimes appears at a 2θ of around 36° in addition to the peak at a 2θ of around 31°. The peak at a 2θ of around 36° is derived from a crystal structure that is classified into the space group Fd-3m; thus, this peak is preferably not exhibited in a CAAC-OS.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray is incident on the CAAC-OS in a direction parallel to the formation surface, a peak appears at a 2θ of around 56°. This peak is attributed to the (110) plane of the InGaZnO₄ crystal. When analysis (ϕ scan) is performed with 2θ fixed at around 560 and with the sample rotated using a normal vector to the sample surface as an axis (ϕ axis), as shown in FIG. 56B, a peak is not clearly observed. In contrast, in the case where single crystal InGaZnO₄ is subjected to ϕ scan with 2θ fixed at around 56°, as shown in FIG. 56C, six peaks that are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in a direction parallel to the formation surface of the CAAC-OS, a diffraction pattern (also referred to as a selected-area electron diffraction pattern) shown in FIG. 56D can be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO₄ crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 56E shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 56E, a ring-like diffraction pattern is observed. Thus, the electron diffraction using an electron beam with a probe diameter of 300 nm also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular orientation. The first ring in FIG. 56E is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 56E is considered to be derived from the (110) plane and the like.

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed in some cases. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

FIG. 57A shows a high-resolution TEM image of a cross section of the CAAC-OS that is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 57A shows pellets in which metal atoms are arranged in a layered manner. FIG. 57A proves that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC). A pellet reflects unevenness of a formation surface or a top surface of the CAAC-OS, and is parallel to the formation surface or the top surface of the CAAC-OS.

FIGS. 57B and 57C show Cs-corrected high-resolution TEM images of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 57D and 57E are images obtained through image processing of FIGS. 57B and 57C. The method of image processing is as follows. The image in FIG. 57B is subjected to fast Fourier transform (FFT), so that an FFT image is obtained. Then, mask processing is performed such that a range of from 2.8 nm⁻¹ to 5.0 nm⁻¹ from the origin in the obtained FFT image remains. After the mask processing, the FFT image is processed by inverse fast Fourier transform (IFFT) to obtain a processed image. The image obtained in this manner is called an FFT filtering image. The FFT filtering image is a Cs-corrected high-resolution TEM image from which a periodic component is extracted, and shows a lattice arrangement.

In FIG. 57D, a portion where a lattice arrangement is broken is denoted with a dashed line. A region surrounded by a dashed line is one pellet. The portion denoted with the dashed line is a junction of pellets. The dashed line draws a hexagon, which means that the pellet has a hexagonal shape. Note that the shape of the pellet is not always a regular hexagon but is a non-regular hexagon in many cases.

In FIG. 57E, a dotted line denotes a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement. A clear crystal grain boundary cannot be observed even in the vicinity of the dotted line. When a lattice point in the vicinity of the dotted line is regarded as a center and surrounding lattice points are joined, a distorted hexagon, pentagon, and/or heptagon can be formed, for example. That is, a lattice arrangement is distorted so that formation of a crystal grain boundary is inhibited. This is probably because the CAAC-OS can tolerate distortion owing to a low density of the atomic arrangement in an a-b plane direction, an interatomic bond distance changed by substitution of a metal element, and the like.

As described above, the CAAC-OS has c-axis alignment, its pellets (nanocrystals) are connected in an a-b plane direction, and the crystal structure has distortion. For this reason, the CAAC-OS can also be referred to as an oxide semiconductor including a c-axis-aligned a-b-plane-anchored (CAA) crystal.

The CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

Next, an nc-OS is described.

Analysis of an nc-OS by XRD is described. When the structure of an nc-OS is analyzed by an out-of-plane method, a peak indicating orientation does not appear. That is, a crystal of an nc-OS does not have orientation.

For example, when an electron beam with a probe diameter of 50 nm is incident on a 34-nm-thick region of thinned nc-OS including an InGaZnO₄ crystal in a direction parallel to the formation surface, a ring-shaped diffraction pattern (a nanobeam electron diffraction pattern) shown in FIG. 58A is observed. FIG. 58B shows a diffraction pattern obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. As shown in FIG. 58B, a plurality of spots are observed in a ring-like region. In other words, ordering in an nc-OS is not observed with an electron beam with a probe diameter of 50 nm but is observed with an electron beam with a probe diameter of 1 nm.

Furthermore, an electron diffraction pattern in which spots are arranged in an approximately regular hexagonal shape is observed in some cases as shown in FIG. 58C when an electron beam having a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm. This means that an nc-OS has a well-ordered region, i.e., a crystal, in the range of less than 10 nm in thickness. Note that an electron diffraction pattern having regularity is not observed in some regions because crystals are aligned in various directions.

FIG. 58D shows a Cs-corrected high-resolution TEM image of a cross section of an nc-OS observed from the direction substantially parallel to the formation surface. In a high-resolution TEM image, an nc-OS has a region in which a crystal part is observed, such as the part indicated by additional lines in FIG. 58D, and a region in which a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or specifically, greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

As described above, in the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.

FIGS. 59A and 59B are high-resolution cross-sectional TEM images of an a-like OS. FIG. 59A is the high-resolution cross-sectional TEM image of the a-like OS at the start of the electron irradiation. FIG. 59B is the high-resolution cross-sectional TEM image of the a-like OS after the electron (e⁻) irradiation at 4.3×10⁸ e/nm². FIGS. 59A and 59B show that stripe-like bright regions extending vertically are observed in the a-like OS from the start of the electron irradiation. It can be also found that the shape of the bright region changes after the electron irradiation. Note that the bright region is presumably a void or a low-density region.

The a-like OS has an unstable structure because it contains a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS, an nc-OS, and a CAAC-OS are prepared as samples. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

It is known that a unit cell of an InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄ in the following description. Each of lattice fringes corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 60 shows change in the average size of crystal parts (at 22 points to 30 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 60 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose in obtaining TEM images, for example. As shown in FIG. 60 , a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 1.9 nm at a cumulative electron (e⁻) dose of 4.2×10⁸ e/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e/nm². As shown in FIG. 60 , the crystal part sizes in an nc-OS and a CAAC-OS are approximately 1.3 nm and approximately 1.8 nm, respectively, regardless of the cumulative electron dose. For the electron beam irradiation and TEM observation, a Hitachi H-9000NAR transmission electron microscope was used. The conditions of electron beam irradiation were as follows: the accelerating voltage was 300 kV; the current density was 6.7×10⁵ e/(nm²·s); and the diameter of irradiation region was 230 nm.

In this manner, growth of the crystal part in the a-like OS is sometimes induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it contains a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that in the case where an oxide semiconductor having a certain composition does not exist in a single crystal structure, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more films of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

Next, the carrier density of an oxide semiconductor is described below.

Examples of a factor affecting the carrier density of an oxide semiconductor include oxygen vacancy (Vo) and impurities in the oxide semiconductor.

As the amount of oxygen vacancy in the oxide semiconductor increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancy (this state is also referred to as VoH). The density of defect states also increases with an increase in the amount of impurity in the oxide semiconductor. Hence, the carrier density of an oxide semiconductor can be controlled by controlling the density of defect states in the oxide semiconductor.

A transistor using the oxide semiconductor in a channel region is described below.

The carrier density of the oxide semiconductor is preferably reduced in order to inhibit the negative shift of the threshold voltage of the transistor or reduce the off-state current of the transistor. In order to reduce the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor is reduced so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. The carrier density of a highly purified oxide semiconductor is lower than 8×10¹⁵ cm³, preferably lower than 1×10¹¹ cm³, and further preferably lower than 1×10¹⁰ cm³ and is higher than or equal to 1×10⁻⁹ cm³.

In contrast, the carrier density of the oxide semiconductor is preferably increased in order to improve the on-state current of the transistor or improve the field-effect mobility of the transistor. In order to increase the carrier density of the oxide semiconductor, the impurity concentration or the density of defect states in the oxide semiconductor is slightly increased. Alternatively, the bandgap of the oxide semiconductor is preferably narrowed. For example, an oxide semiconductor that has a slightly high impurity concentration or a slightly high density of defect states in the range where a favorable on/off ratio is obtained in the I_(d)-V_(g) characteristics of the transistor can be regarded as substantially intrinsic. Furthermore, an oxide semiconductor that has a high electron affinity and thus has a narrow bandgap so as to increase the density of thermally excited electrons (carriers) can be regarded as substantially intrinsic. Note that a transistor using an oxide semiconductor with higher electron affinity has lower threshold voltage.

The aforementioned oxide semiconductor with an increased carrier density has somewhat n-type conductivity; thus, it can be referred to as a “slightly-n” oxide semiconductor.

The carrier density of a substantially intrinsic oxide semiconductor is preferably higher than or equal to 1×10⁵ cm⁻³ and lower than 1×10¹⁸ cm⁻³, further preferably higher than or equal to 1×10⁷ cm⁻³ and lower than or equal to 1×10¹⁷ cm⁻³, still further preferably higher than or equal to 1×10⁹ cm⁻³ and lower than or equal to 5×10¹⁶ cm⁻³, yet further preferably higher than or equal to 1×10¹⁰ cm⁻³ and lower than or equal to 1×10¹⁶ cm⁻³, and yet still preferably higher than or equal to 1×10¹¹ cm⁻³ and lower than or equal to 1×10¹⁵ cm⁻³.

The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

Embodiment 8

In this embodiment, examples of a package and a module each including an image sensor chip are described. The image sensor chip can employ the configuration of the imaging device of one embodiment of the present invention.

FIG. 61A is an external perspective view showing the top surface side of a package including an image sensor chip. The package includes a package substrate 810 to which an image sensor chip 850 is fixed, a cover glass 820, an adhesive 830 for bonding the package substrate 810 and the cover glass 820 to each other, and the like.

FIG. 61B is an external perspective view showing the bottom surface side of the package. The package has a ball grid array (BGA) structure including solder balls as bumps 840 on the bottom surface. Instead of the BGA, a land grid array (LGA), a pin grid array (PGA), or the like may be employed.

FIG. 61C is a perspective view of the package in which the cover glass 820 and the adhesive 830 are partly illustrated. FIG. 61D is a cross sectional view of the package. Electrode pads 860 are formed over the package substrate 810, and the electrode pads 860 and the bumps 840 are electrically connected via through holes 880 and lands 885. The electrode pads 860 are electrically connected to electrodes of the image sensor chip 850 through wires 870.

FIG. 62A is an external perspective view showing the top surface side of a camera module in which an image sensor chip and a lens integrated with each other in a package. The camera module includes a package substrate 811 to which an image sensor chip 851 is fixed, a lens cover 821, a lens 835, and the like. Furthermore, an IC chip 890 having functions of a driver circuit, a signal conversion circuit, and the like of an imaging device is provided between the package substrate 811 and the image sensor chip 851. Thus, a system in package (SiP) is formed.

FIG. 62B is an external perspective view showing the bottom surface side of the camera module. Here, a quad flat no-lead package (QFN) is employed in which mounting lands 841 are provided on the bottom surface and four side surfaces of the package substrate 811. This structure is only an example; a quad flat package (QFP), the above-described BGA, or the like may be alternatively employed.

FIG. 62C is a perspective view of the module in which the lens cover 821 and the lens 835 are partly illustrated. FIG. 62D is a cross-sectional view of the camera module. Some of the lands 841 are used as the electrode pads 861. The electrode pads 861 are electrically connected to electrodes of the image sensor chip 851 and the IC chip 890 through wires 871.

The image sensor chip can be easily mounted on the package having the above structure, and can be incorporated into a variety of semiconductor devices and electronic devices.

The structures described in this embodiment can be used in appropriate combination with any of the structures described in the other embodiments.

Embodiment 9

This embodiment show examples of electronic devices in which an imaging device of one embodiment of the present invention is used.

Examples of electronic devices to which the imaging device of one embodiment of the present invention can be applied are display devices such as televisions and monitors, lighting devices, desktop personal computers and laptop personal computers, word processors, image reproduction devices that reproduce still images and moving images stored in recording media such as digital versatile discs (DVD), portable CD players, radios, tape recorders, headphone stereos, stereos, navigation systems, table clocks, wall clocks, cordless phone handsets, transceivers, mobile phones, car phones, portable game consoles, tablet terminals, large game machines such as pinball machines, calculators, portable information terminals, electronic notebooks, e-book readers, electronic translators, audio input devices, video cameras, digital still cameras, electric shavers, high-frequency heating appliances such as microwave ovens, electric rice cookers, electric washing machines, electric vacuum cleaners, water heaters, electric fans, hair dryers, air-conditioning systems such as air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, freezers for preserving DNA, flashlights, electric power tools such as chain saws, smoke detectors, medical equipment such as dialyzers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines. Furthermore, industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, and power storage devices for leveling the amount of power supply and smart grid can be given. In addition, moving objects driven by an electric motor using electric power are also included in the category of electronic devices. Examples of the moving objects are electric vehicles (EV), hybrid electric vehicles (HEV) that include both an internal-combustion engine and a motor, plug-in hybrid electric vehicles (PHEV), tracked vehicles in which caterpillar tracks are substituted for wheels of these vehicles, motorized bicycles including motor-assisted bicycles, motorcycles, electric wheelchairs, golf carts, boats, ships, submarines, helicopters, aircrafts, rockets, artificial satellites, space probes, planetary probes, and spacecrafts.

FIG. 63A illustrates a robot arm including a base 921, an arm 922, a joint 923, an arm end 924, a sensor 925, and the like. The sensor 925 senses the position or shape of an object, and the arm end 924 grasps and carries the object. The imaging device of one embodiment of the present invention can be used for the sensor 925.

FIG. 63B illustrates an inspection apparatus including a housing 931, a sensor 932, and the like. The inspection apparatus is configured to detect a fault in a product 934 on a conveyor belt 933, for example. The imaging device of one embodiment of the present invention can be used for the sensor 932.

FIG. 63C illustrates an eyeball including a retina 941, a lens 942, an optic nerve 943, and the like. A sensor 944 is embedded in the retina 941 and can serve as the retina 941 when the retina 941 loses a function of converting visual information into an electrical signal, which leads to recovery in vision. The imaging device of one embodiment of the present invention can be used for the sensor 944.

FIG. 63D illustrates a monitoring camera, which includes a housing 951, a lens 952, a support portion 953, and the like. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the monitoring camera. Note that a “monitoring camera” is a common name and does not limit the uses. For example, a device that has a function of a monitoring camera can also be called a camera or a video camera.

FIG. 63E illustrates a wrist-watch-type information terminal, which includes a housing 961, a display portion 962, a wristband 963, operation buttons 965, a winder 966, a camera 969, and the like. The display portion 962 may be a touch panel. The imaging device of one embodiment of the present invention can be included as a component for obtaining an image in the information terminal.

FIG. 63F illustrates a portable data terminal, which includes a first housing 971, a display portion 972, a camera 979, and the like. A touch panel function of the display portion 972 enables input and output of information. The imaging device of one embodiment of the present invention can be included as one component for obtaining an image in the portable data terminal.

The examples are not limited to the above-described electronic devices as long as the imaging device of one embodiment of the present invention is included.

This embodiment can be combined with any of the other embodiments in this specification as appropriate.

This application is based on Japanese Patent Application serial No. 2015-161851 filed with Japan Patent Office on Aug. 19, 2015, the entire contents of which are hereby incorporated by reference. 

1. (canceled)
 2. An imaging device comprising: a pixel comprising: a first photoelectric conversion element; a second photoelectric conversion element; and a first transistor, wherein an anode of the first photoelectric conversion element is directly connected to an anode of the second photoelectric conversion element, and wherein one of a source and a drain of the first transistor is electrically connected to a cathode of the first photoelectric conversion element.
 3. The imaging device according to claim 2, wherein the first transistor is an n-channel transistor.
 4. The imaging device according to claim 2, wherein the first transistor comprises an oxide semiconductor, and wherein the oxide semiconductor comprises indium and zinc.
 5. The imaging device according to claim 2, wherein the other of the source and the drain of the first transistor is electrically connected to a first node, and wherein the first transistor is configured to control the accumulation of charge from the first photoelectric conversion element and the second photoelectric conversion element to the first node.
 6. The imaging device according to claim 2, wherein each of the first photoelectric conversion element and the second photoelectric conversion element comprises selenium.
 7. The imaging device according to claim 2, wherein a cathode of the second photoelectric conversion element is electrically connected to a first wiring.
 8. An imaging device comprising: a pixel comprising: a first photoelectric conversion element; a second photoelectric conversion element; a first transistor; a second transistor; and a third transistor, wherein an anode of the first photoelectric conversion element is directly connected to an anode of the second photoelectric conversion element, wherein one of a source and a drain of the first transistor is electrically connected to a cathode of the first photoelectric conversion element, and wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor.
 9. The imaging device according to claim 8, wherein each of the first transistor, the second transistor, and the third transistor is an n-channel transistor.
 10. The imaging device according to claim 8, wherein each of the first transistor, the second transistor, and the third transistor comprises an oxide semiconductor, and wherein the oxide semiconductor comprises indium and zinc.
 11. The imaging device according to claim 8, wherein the other of the source and the drain of the first transistor is electrically connected to a first node, and wherein the first transistor is configured to control the accumulation of charge from the first photoelectric conversion element and the second photoelectric conversion element to the first node.
 12. The imaging device according to claim 8, wherein each of the first photoelectric conversion element and the second photoelectric conversion element comprises selenium.
 13. The imaging device according to claim 8, wherein a cathode of the second photoelectric conversion element is electrically connected to a first wiring. 